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TC59LM836DKB-30 Datasheet(PDF) 1 Page - Toshiba Semiconductor |
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TC59LM836DKB-30 Datasheet(HTML) 1 Page - Toshiba Semiconductor |
1 / 65 page TC59LM836DKB-30,-33,-40 2005-03-07 1/65 Rev 1.3 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 288Mbits Network FCRAM2 − 2,097,152-WORDS × 4 BANKS × 36-BITS DESCRIPTION Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM836DKB is Network FCRAMTM containing 301,989,888 memory cells. TC59LM836DKB is organized as 2,097,152-words × 4 banks × 36 bits. TC59LM836DKB feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. TC59LM836DKB can operate fast core cycle compared with regular DDR SDRAM. TC59LM836DKB is suitable for Network and other applications where large memory density and low power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data transfer under light loading condition. FEATURES TC59LM836DKB PARAMETER -30 -33 -40 CL = 4 4.0 ns 4.5 ns 5.0 ns CL = 5 3.5 ns 3.75 ns 4.5 ns tCK Clock Cycle Time (min) CL = 6 3.0 ns 3.33 ns 4.0 ns tRC Random Read/Write Cycle Time (min) 20.0 ns 22.5 ns 25 ns tRAC Random Access Time (max) 20.0 ns 22.5 ns 25 ns IDD1S Operating Current (single bank) (max) 380 mA 360 mA 340 mA lDD2P Power Down Current (max) 100 mA 95 mA 90 mA lDD6 Self-Refresh Current (max) 15 mA 15 mA 15 mA • Fully Synchronous Operation • Double Data Rate (DDR) Data input/output are synchronized with both edges of DS / QS. • Differential Clock (CLK and CLK ) inputs CS , FN and all address input signals are sampled on the positive edge of CLK. Output data (DQs and QS) is aligned to the crossings of CLK and CLK . • Fast clock cycle time of 3.0 ns minimum Clock: 333 MHz maximum Data: 666 Mbps/pin maximum • Quad Independent Banks operation • Fast cycle and Short Latency • Selectable Data Strobe • Distributed Auto-Refresh cycle in 3.9 µs • Self-Refresh • Power Down Mode • Variable Write Length Control • Write Latency = CAS Latency-1 • Programable CAS Latency and Burst Length CAS Latency = 4, 5, 6 Burst Length = 2, 4 • Organization: 2,097,152 words × 4 banks × 36 bits • Power Supply Voltage VDD: 2.5 V ± 0.125V VDDQ: 1.4 V ~ 1.9 V • Low voltage CMOS I/O covered with SSTL_18 (Half strength driver) and HSTL. • JTAG boundary scan • Package: 144Ball BGA, 1mm × 0.8mm Ball pitch (P-TFBGA144-1119-0.80BZ) Notice: FCRAM is trademark of Fujitsu limited, Japan. |
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