TC59LM914AMG-50 datasheet(6/59 Pages) TOSHIBA

No. de pieza	TC59LM914AMG-50

Descripción Electrónicos	MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

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Fabricante Electrónico	TOSHIBA [Toshiba Semiconductor]

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6 / 59 page

TC59LM914/06AMG-37,-50

2004-08-20

6/59

Rev 1.0

Note:

(1) All voltages referenced to VSS, VSSQ.

(2) VREF is expected to track variations in VDDQ DC level of the transmitting device.

Peak to peak AC noise on VREF may not exceed ±2% VREF (DC).

(3) Overshoot limit: VIH (max) = VDDQ + 0.7 V with a pulse width ≤ 5 ns.

(4) Undershoot limit: VIL (min) = −0.7 V with a pulse width ≤ 5 ns.

(5) VIH (DC) and VIL (DC) are levels to maintain the current logic state.

(6) VIH (AC) and VIL (AC) are levels to change to the new logic state.

(7) VID is magnitude of the difference between VTR input level and VCP input level.

(8) The value of VX (AC) is expected to equal VDDQ/2 of the transmitting device.

(9) VISO means {VICK (VTR) + VICK (VCP)} /2.

(10) Refer to the figure below. VTR is the true input (such as CLK, DQS) level and VCP is the complementary

input (such as CLK ,

DQS ) level.

(11) In the case of external termination, VTT (termination voltage) should be gone in the range of VREF (DC) ±

0.04 V.

CAPACITANCE (VDD = 2.5V, VDDQ = 1.8 V, f = 1 MHz, Ta = 25°C)

SYMBOL

PARAMETER

MIN

MAX

Delta

UNIT

CIN

Input pin Capacitance

1.5

2.5

0.25

pF

CINC

Clock pin (CLK, CLK ) Capacitance

1.5

2.5

0.25

pF

CI/O

DQ, DQS, UDQS, LDQS, DQS Capacitance

2.5

4

0.5

pF

CNC

NC pin Capacitance

⎯

4

⎯

pF

Note: These parameters are periodically sampled and not 100% tested.

VISO (min)

VISO (max)

VICK

Vx

VICK

CLK

VSS

|VID (AC)|

0 V Differential

VISO

VSS

VID (AC)

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