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TC74AC139P Datasheet(PDF) 1 Page - Toshiba Semiconductor |
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TC74AC139P Datasheet(HTML) 1 Page - Toshiba Semiconductor |
1 / 9 page TC74AC139P/F/FN/FT 2007-10-01 1 TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC139P,TC74AC139F,TC74AC139FN,TC74AC139FT Dual 2-to-4 Line Decoder The TC74AC139 is an advanced high speed CMOS 2-to-4 LINE DECODER fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The active low enable input can be used for gating or it can be used as a data input for demultiplexing applications. When the enable input is held “H”, all four outputs are fixed at a high logic level independent of the other inputs. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: tpd = 5.9 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 8 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines. • Balanced propagation delays: tpLH ∼− tpHL • Wide operating voltage range: VCC (opr) = 2 V to 5.5 V • Pin and function compatible with 74F139 Pin Assignment Note: xxxFN (JEDEC SOP) is not available in Japan. TC74AC139P TC74AC139F TC74AC139FN TC74AC139FT Weight DIP16-P-300-2.54A : 1.00 g (typ.) SOP16-P-300-1.27A : 0.18 g (typ.) SOL16-P-150-1.27 : 0.13 g (typ.) TSSOP16-P-0044-0.65A : 0.06 g (typ.) (top view) VCC 16 2A 2B 15 14 13 12 11 10 1 2 3 4 5 6 7 GND 8 9 1A 1B G 1 0 Y 1 1 Y 1 2 Y 1 3 Y 1 G 2 0 Y 2 1 Y 2 2 Y 2 3 Y 2 |
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