TC74HCT74AP_07 datasheet(4/8 Pages) TOSHIBA

No. de pieza	TC74HCT74AP

Descripción Electrónicos	Dual D-Type Flip Flop with Preset and Clear

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Fabricante Electrónico	TOSHIBA [Toshiba Semiconductor]

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TC74HCT74AP/AF/AFN

2007-10-01

4

Timing Requirements (input: tr = tf = 6 ns)

Test Condition

Ta

= 25°C

Ta

=

−40

~85°C

Characteristics

Symbol

VCC (V)

Typ.

Limit

Unit

Minimum pulse width

(CK)

tW (L)

tW (H)

⎯

4.5

5.5

⎯

15

14

19

17

ns

Minimum pulse width

( CLR , PR )

tW (L)

⎯

4.5

5.5

⎯

15

14

19

17

ns

Minimum set-up time

ts

⎯

4.5

5.5

⎯

15

14

19

17

ns

Minimum hold time

th

⎯

4.5

5.5

⎯

0

ns

Minimum removal time

( CLR , PR )

trem

⎯

4.5

5.5

⎯

5

ns

Clock frequency

f

⎯

4.5

5.5

⎯

27

30

22

24

MHz

AC Characteristics (CL = 15 pF, VCC = 5 V, Ta = 25°C, input: tr = tf = 6 ns)

Characteristics

Symbol

Test Condition

Min

Typ.

Max

Unit

Output transition time

tTLH

tTHL

⎯

6

12

ns

Propagation delay time

(CK-Q, Q )

tpLH

tpHL

⎯

17

28

ns

Propagation delay time

( CLR , PR -Q, Q )

tpLH

tpHL

⎯

15

25

ns

Maximum clock frequency

fmax

⎯

29

53

⎯

MHz

AC Characteristics (CL = 50 pF, input: tr = tf = 6 ns)

Test Condition

Ta

= 25°C

Ta

= −40~85°C

Characteristics

Symbol

VCC (V)

Min

Typ.

Max

Min

Max

Unit

Output transition time

tTLH

tTHL

⎯

4.5

5.5

⎯

8

7

15

13

⎯

19

16

ns

Propagation delay

time

(CK-Q, Q )

tpLH

tpHL

⎯

4.5

5.5

⎯

21

19

33

30

⎯

41

37

ns

Propagation delay

time

( CLR , PR -Q, Q )

tpLH

tpHL

⎯

4.5

5.5

⎯

18

15

30

27

⎯

38

35

ns

Maximum clock

frequency

fmax

⎯

4.5

5.5

27

30

48

53

⎯

22

24

⎯

MHz

Input capacitance

CIN

⎯

5

10

⎯

10

pF

Power dissipation

capacitance

CPD

(Note)

⎯

32

⎯

pF

Note:

CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating

current consumption without load.

Average operating current can be obtained by the equation:

ICC (opr) = CPD･VCC･fIN + ICC/2 (per F/F)

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