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SN74AUC1G74YEPR Datasheet(PDF) 2 Page - Texas Instruments |
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SN74AUC1G74YEPR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 12 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) TG C C TG C C TG C C C TG C C CLR CLK D PRE Q Q C 6 2 7 3 5 1 SN74AUC1G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES537A – DECEMBER 2003 – REVISED AUGUST 2005 This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L X L X X L H H H ↑ H H L H H ↑ L L H H H L X Q0 Q 0 LOGIC DIAGRAM (POSITIVE LOGIC) 2 |
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