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TC9327BFG Datasheet(PDF) 11 Page - Toshiba Semiconductor |
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TC9327BFG Datasheet(HTML) 11 Page - Toshiba Semiconductor |
11 / 71 page TC9327BFG 2005-04-20 11 5. Data Memory (RAM) The data memory consists of 4 bits × 256 words and is used for storing data. These 256 words are expressed in row addresses (4 bits) and column addresses (4 bits). 192 words (row address = addresses 4H to FH) within the data memory are addressed indirectly by the G-register. Owing to this, it is necessary to specify the row address with the G-register before the data in this area can be processed. The addresses 00H to 0FH within the data memory are known as general registers, and these can be used simply by specifying the relevant column addresses (4 bit). These sixteen general registers can be used for operations and transfers with the data memory, and may also be used as normal data memories. Note 7: The column address (4 bit) that specifies the general register is the register number of the general register. Note 8: All row addresses (addresses 0H to FH) can be specified indirectly with the G-register. Note 9: The indirect specification of row addresses = 0H to FH is also possible 6. G-Register (G-REG) The G-register is a 4 bit register used for addressing the row addresses (DR = 4H to FH addresses) of the data memory’s 192 words. The contents of this register are validated when the MVGD instruction or MVGS instruction are executed, and are not affected through the execution of any other instructions. This register is used as one of the ports, and the contents are set when the OUT1 instruction from amongst the I/O instructions is executed. ( → refer to section #1 in register ports.) 7. Data Register (DATA REG) The data register consists of 1 × 16 bits and loads 16 bits of optional address data from amongst addresses 000H to 3FFH in the program memory when the DAL instruction is executed. This register is used as one of the ports, and the contents are loaded into the data memory in units of 4 bits when the IN1 instruction from amongst the I/O instructions is executed. ( → refer to section #2 in register ports.) 8. Carry F/F (CF/F) This is set when either CARRY or BORROW are issued in the result of calculation instruction execution and is reset if neither of these are issued. The contents of carry F/F can only be amended through the execution of addition or subtraction instructions and are not affected by the execution of any other instruction. |
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