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74LVQ174T Datasheet(PDF) 1 Page - STMicroelectronics |
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74LVQ174T Datasheet(HTML) 1 Page - STMicroelectronics |
1 / 10 page 74LVQ174 HEX D-TYPE FLIP FLOP WITH CLEAR ® February 1999 s HIGH SPEED: fMAX = 150 MHz (TYP.) at VCC = 3.3V s COMPATIBLE WITH TTL OUTPUTS s LOW POWER DISSIPATION: ICC =4 µA (MAX.) at TA =25 oC s LOW NOISE: VOLP = 0.3 V (TYP.) at VCC =3.3V s 75 Ω TRANSMISSION LINE DRIVING CAPABILITY s SYMMETRICAL OUTPUT IMPEDANCE: |IOH|=IOL = 12 mA (MIN) s PCI BUS LEVELS GUARANTEED AT 24mA s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 3.6V (1.2V Data Retention) s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 174 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The LVQ174 is a low voltage CMOS HEX D-TYPE FLIP FLOP WITH CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. It is ideal for low power and low noise 3.3V applications. Information signals applied to D inputs are transfered to the Q outputs on the positive going edge of the clock pulse. When the CLEAR input is held low, the Q outputs are held low independentely of the other inputs . It has better speed performance at 3.3V than 5V LS-TTL family combined with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS M (Micro Package) T (TSSOP Package) ORDER CODES : 74LVQ174M 74LVQ174T 1/10 |
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