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SN74AUP1G57DRLR Datasheet(PDF) 2 Page - Texas Instruments |
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SN74AUP1G57DRLR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 18 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) 3 1 6 In2 In1 In0 4 Y SN74AUP1G57 LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE SCES503G – NOVEMBER 2003 – REVISED APRIL 2007 This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION ORDERABLE PART TA PACKAGE(1)(2) TOP-SIDE MARKING(3) NUMBER NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YFP Reel of 3000 SN74AUP1G57YFPR PREVIEW (Pb-free) NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP Reel of 3000 SN74AUP1G57YZPR _ _ _HH_ (Pb-free) –40 °C to 85°C SON – DRY Reel of 5000 SN74AUP1G57DRYR PREVIEW SOT (SOT-23) – DBV Reel of 3000 SN74AUP1G57DBVR HA7_ SOT (SC-70) – DCK Reel of 3000 SN74AUP1G57DCKR HH_ SOT (SOT-553) – DRL Reel of 4000 SN74AUP1G57DRLR HH_ (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. (2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. (3) DBV/DCK/DRL/DRY: The actual top-side marking has one additional character that designates the assembly/test site. YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE INPUTS OUTPUT Y In2 In1 In0 L L L H L L H L L H L H L H H L H L L L H L H L H H L H H H H H LOGIC DIAGRAM (POSITIVE LOGIC) 2 Submit Documentation Feedback |
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