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TMP3C6414CGLZ5E0 Datasheet(PDF) 4 Page - Texas Instruments |
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TMP3C6414CGLZ5E0 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 139 page TMS320C6414, TMS320C6415, TMS320C6416 FIXEDPOINT DIGITAL SIGNAL PROCESSORS SPRS146L − FEBRUARY 2001 − REVISED JULY 2004 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PAGE(S) NO. ADDITIONS/CHANGES/DELETIONS 87−88 Asynchronous Memory Timing section: Timing Requirements for Asynchronous Memory Cycles for EMIFA Module table: Added/split silicon revisions “Rev 1.1 and earlier” and “Rev 2.0” for the MIN value of parameter #7 “th(EKO1H-ARDY), Hold time, ARDY valid after ECLKOUTx high” Added under the “−5E0, −6E3, −7E3” column, the MIN value of “1.3” ns for “Rev 2.0” Timing Requirements for Asynchronous Memory Cycles for EMIFB Module table: Added/split silicon revisions “Rev 1.1 and earlier” and “Rev 2.0” for the MIN value of parameter #7 “th(EKO1H-ARDY), Hold time, ARDY valid after ECLKOUTx high” Added under the “−5E0, −6E3, −7E3” column, the MIN value of “1.3” ns for “Rev 2.0” 106 HOLD/HOLDA Timing section: Timing Requirements for the HOLD/HOLDA Cycles for EMIFA and EMIFB modules table: Changed parameter NO. 3 from “toh(HOLDAL-HOLDL)” to “th(HOLDAL-HOLDL)” 108 Reset Timing section: Timing Requirements for Reset table: Changed the MIN value of parameter No. 16, tsu(boot) from “4P” to “4E or 4C” ns Added associated footnote to identify “E” and “C” Added parameter NO. 18, “td(PCLK−RSTH) Delay time, PCLK active to RESET high” with a MIN value of “32N” ns Changed parameter NO. 18 description from “td(PCLK−RSTH) Delay time, PCLK active to RESET high” to “tsu(PCLK-RSTH), Setup time, PCLK active before RESET high” Added associated footnote to identify “N” and restraints Switching Characteristics Over Recommended Operating Conditions During Reset table: Moved parameter NO. 18, “td(PCLK−RSTH) Delay time, PCLK active to RESET high” to the Timing Requirements for Reset table Updated footnote symbols 111 Host-Port Interface (HPI) Timing section: Switching Characteristics Over Recommended Operating Conditions During Host-Port Interface Cycles table: Added “mode, 2nd half-word” to parameter NO. 16 “td(HSTBL-HDV), Delay time, HSTROBE low to HD valid (HPI16 only)” 118 Peripheral Component Interconnect (PCI) Timing [C6415 AND C6416 ONLY] section: Switching Characteristics Over Recommended Operating Conditions for Serial EEPROM Interface table: Changed parameter NO. 6 description from “tosu(DOV-CLKH), Output setup time, XSP_DO valid after XSP_CLK high” to “tosu(DOV-CLKH), Output setup time, XSP_DO valid before XSP_CLK high” 120−121 Multichannel Buffered Serial Port (McBSP) Timing section: Switching Characteristics Over Recommended Operating Conditions for McBSP table: Changed the MIN value of parameter #12 “tdis(CKXH-DXHZ), Disable time, DX high impedance following last data bit from CLKX high, CLKX ext” from “−2.1” to “2.0” ns Changed the MIN value of parameter #13 “td(CKXH-DXV), Delay time, CLKX high to DX valid, CLKX ext” from “−2.1 + D1” to “2.0 + D1” ns Changed the MIN value of parameter #14 “td(FXH-DXV), Delay time, FSX high to DX valid, FSX int” from “−2.3” to “−2.3 + D1h” ns Changed the MAX value of parameter #14 “td(FXH-DXV), Delay time, FSX high to DX valid, FSX int” from “5.6” to “5.6 + D2h” ns Changed the MIN value of parameter #14 “td(FXH-DXV), Delay time, FSX high to DX valid, FSX ext” from “1.9” to “1.9 + D1h” ns Changed the MAX value of parameter #14 “td(FXH-DXV), Delay time, FSX high to DX valid, FSX ext” from “9” to “9 + D2h” ns Added associated footnote Figure 51, McBSP Timing: Added footnote for clarity |
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