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CB45000 Datasheet(PDF) 3 Page - STMicroelectronics |
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CB45000 Datasheet(HTML) 3 Page - STMicroelectronics |
3 / 16 page 3/16 CB45000 SERIES ® TECHNOLOGY OVERVIEW A major feature of the HCMOS6 process is salicided active areas. This results in source drain areas that are on the order of one to two ohms resistance as opposed to the hundreds or thousands of ohms of source drain resistance in non-salicided technologies. This very low resistance is one reason that very low transistor widths could be utilized in the cell design since drive is not lost due to source drain resistance. This use of low width transistors results in lower capacitance loading of the gates due to the smaller areas utilized. Low resistance, low capacitance, and small gates results in low power usage for inverters as compared to previous technologies. The reduction in power consumption allows the usage of salicided active stripes to distribute power internally to the simple cell, replacing, in some cases, the usage of the first metal layer. This saves silicon area by allowing greater density, permeability and routability of the cells resulting in greater overall circuit density. The other major feature of the HCMOS6 process is five metal layer interconnect using CMP (Chemical Mechanical Polishing) planarization. The use of CMP for improved planarity between metal layers allows the use of additional interconnect layers without yield degradation, improving density whilst retaining low costs. The power distribution methodology provides separate internal distributions to improve product noise margin and reduce power loss. The three supplies are: s Internal Vdd and Vss Serves the core cells and the prebuffer sec- tions of the I/O s External Vdd and Vss Serves the output transistors only s Receiver Vdd and Vss Serves the first stages of the receiver cells. Optional distributions for 5.0V interface and other standards can be utilized as necessary. |
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