The following specifications apply to the ADC12048 for V

sion mode, f

Ω, source impedance for V

≤ 1Ω, fully differential input with fixed 2.048V

common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T

to T

Symbol

Parameter

Conditions

Typical

Limits

Unit

(Note 10)

(Note 11)

(Limit)

C

REF

Reference Input

Capacitance

85

pF

Digital Logic Input/Output Characteristics

The following specifications apply to the ADC12048 for V

sion mode, f

Ω, source impedance for V

≤ 1Ω, fully differential input with fixed 2.048V

common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T

to T

Symbol

Parameter

Conditions

Typical

Limits

Unit

(Note 10)

(Note 11)

(Limit)

V

IH

Logic High Input Voltage

V

2.0

V (min)

V

IL

Logic Low Input Voltage

V

0.8

V (max)

I

IH

Logic High Input Current

V

0.035

2.0

µA (max)

I

IL

Logic Low Input Current

V

−0.035

−2.0

µA (max)

V

OH

Logic High Output Voltage

V

2.4

V (min)

I

V

OL

Logic Low Output Voltage

V

0.4

V (max)

I

I

OFF

Leakage Current

V

V

µA (max)

C

IN

D12–D0 Input Capacitance

10

pF

Converter AC Characteristics

The following specifications apply to the ADC12048 for V

sion mode, f

Ω, source impedance for V

≤ 1Ω, fully differential input with fixed 2.048V

common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T

to T

Symbol

Parameter

Conditions

Typical

Limits

Unit

(Note 10)

(Note 11)

(Limit)

t

Z

Auto Zero Time

78

78 clks + 120 ns

clks (max)

t

CAL

Full Calibration Time

4946

4946 clks + 120 ns

clks (max)

CLK Duty Cycle

50

%

40

% (min)

60

% (max)

t

CONV

Conversion Time

Sync-Out Mode

44

44

clks (max)

t

AcqSYNCOUT

Acquisition Time

(Programmable)

Minimum for 13 Bits

9

9 clks + 120 ns

clks (max)

Maximum for 13 Bits

79

79 clks + 120 ns

clks (max)

Digital Timing Characteristics

The following specifications apply to the ADC12048, 13-bit data bus width, V

= 50 pF on data I/O lines

Symbol

Parameter

Conditions

Typical

Limits

Units

(Note 10)

(Note 11)

(Limit)

t

TPR

Throughput Rate

Sync-Out Mode (SYNC Bit =

“0”) 9 Clock Cycles of

Acquisition Time

222

kHz

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