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ADC12048CIVF Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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ADC12048CIVF Datasheet(HTML) 3 Page - National Semiconductor (TI) |
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3 / 32 page  Pin Description (Continued) PLCC Pkg. PQFP Pkg. Pin Name Description Pin Number Pin Number 12 6 V REF− Negative reference input. The operating voltage range for this input is 0V ≤ V REF− ≤ V REF+ −1 (see Figure 3 and 4). This pin should be bypassed to AGND at least with a parallel combination of a 10 µF and a 0.1 µF (ceramic) capacitor. The capacitors should be placed as close to the part as possible. 19 13 MUX OUT− The inverting (negative) and non-inverting (positive) outputs of the multiplexer. The analog inputs to the MUX selected by bits b3–b0 of the Configuration register appear at these pins. 21 15 MUX OUT+ 20 14 ADCIN− ADC inputs. The inverting (negative) and non-inverting (positive) inputs into the ADC. 22 16 ADCIN+ 24 18 WMODE The logic state of this pin at power-up determines which edge of the write signal (WR) will latch in data from the data bus. If tied low, the ADC12048 will latch in data on the rising edge of the WR signal. If tied to a logic high, data will he latched in on the falling edge of the WR signal. The state of this pin should not be changed after power-up. 25 19 SYNC The SYNC pin can be programmed as an input or an output. The Configuration register’s bit b8 controls the function of this pin. When programmed as an input pin (b8 = 1), a rising edge on this pin causes the ADC’s sample-and-hold to hold the analog input signal and begin conversion. When programmed as an output pin (b8 = 0), the SYNC pin goes high when a conversion begins and returns low when completed. 26–31 20–25 D0–D5 13-bit Data bus of the ADC12048. D12 is the most significant bit and D0 is the least significant. The BW (bus width) bit of the Configuration register (b12) selects between an 8-bit or 13-bit data bus width. When the BW bit is cleared (BW = 0), D7–D0 are active and D12–D8 are always in TRI-STATE. When the BW bit is set (BW = 1), D12–D0 are active. 34–40 29–34 D6–D12 43 37 CLK The clock input pin used to drive the ADC12048. The operating range is 0.05 MHz to 12 MHz. 44 38 WR WR is the active low WRITE control input pin. A logic low on this pin and the CS will enable the input buffers of the data pins D12–D0. The signal at this pin is used by the ADC12048 to latch in data on D12–D0. The sense of the WMODE pin at power-up will determine which edge of the WR signal the ADC12048 will latch in data. See WMODE pin description. 139 RD RD is the active low read control input pin. A logic low on this pin and CS will enable the active output buffers to drive the data bus. 240 CS CS is the active low Chip Select input pin. Used in conjunction with the WR and RD signals to control the active data bus input/output buffers of the data bus. 3 41 RDY RDY is an active low output pin. The signal at this pin indicates when a requested function has begun or ended. Refer to section Functional Description and the digital timing diagrams for more detail. 4 42 STDBY This is the standby active low output pin. This pin is low when the ADC12048 is in the standby mode and high when the ADC12048 is out of the standby mode or has been requested to leave the standby mode. 10 4 V A+ Analog supply input pin. The device operating supply voltage range is +5V ±10%. Accuracy is guaranteed only if the V A+ and VD+ are connected to the same potential. This pin should be bypassed to AGND with a parallel combination of a 10 µF and a 0.1 µF (ceramic) capacitor. The capacitors should be placed as close to the supply pins of the part as possible. www.national.com 3 |
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