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SM320VC5506GHH Datasheet(PDF) 11 Page - Texas Instruments |
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SM320VC5506GHH Datasheet(HTML) 11 Page - Texas Instruments |
11 / 120 page Features 11 October 2006 − Revised January 2008 SPRS375C 1 TMS320VC5506 Features D High-Performance, Low-Power, Fixed-Point TMS320C55x Digital Signal Processor − 9.26-ns Instruction Cycle Time − 108-MHz Clock Rate − One/Two Instruction(s) Executed per Cycle − Dual Multipliers [Up to 216 Million Multiply-Accumulates per Second (MMACS)] − Two Arithmetic/Logic Units (ALUs) − Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses D 64K x 16-Bit On-Chip RAM, Composed of: − 64K Bytes of Dual-Access RAM (DARAM) 8 Blocks of 4K × 16-Bit − 64K Bytes of Single-Access RAM (SARAM) 8 Blocks of 4K × 16-Bit D On-Chip Bootloader D 8M × 16-Bit Maximum Addressable External Memory Space (Synchronous DRAM) D 16-Bit External Memory Interface (EMIF) With GPIO Capabilities and Glueless Interface to: − Asynchronous Static RAM (SRAM) − Asynchronous EPROM − Synchronous DRAM (SDRAM) D Programmable Low-Power Control of Six Device Functional Domains D On-Chip Scan-Based Emulation Logic D On-Chip Peripherals − Two 20-Bit Timers − Watchdog Timer − Six-Channel Direct Memory Access (DMA) Controller − Three Multichannel Buffered Serial Ports (McBSPs) − Programmable Phase-Locked Loop Clock Generator − Seven (LQFP) or Eight (BGA) General- Purpose I/O (GPIO) Pins and a General- Purpose Output Pin (XF) − USB Full-Speed (12 Mbps) Slave Port Supporting Bulk, Interrupt and Isochronous Transfers − Inter-Integrated Circuit (I2C) Multi-Master and Slave Interface − Real-Time Clock (RTC) With Crystal Input, Separate Clock Domain, Separate Power Supply D IEEE Std 1149.1† (JTAG) Boundary Scan Logic D Packages: − 144-Terminal Low-Profile Quad Flatpack (LQFP) (PGE Suffix) − 179-Terminal MicroStar BGA (Ball Grid Array) (GHH and ZHH Suffixes) D 1.2-V Core (108 MHz), 2.7-V – 3.6-V I/Os All trademarks are the property of their respective owners. TMS320C55x and MicroStar BGA are trademarks of Texas Instruments. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. |
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