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M27W400-120K6TR Datasheet(PDF) 5 Page - STMicroelectronics

No. de pieza M27W400-120K6TR
Descripción Electrónicos  4 Mbit 512Kb x8 or 256Kb x16 Low Voltage UV EPROM and OTP EPROM
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M27W400-120K6TR Datasheet(HTML) 5 Page - STMicroelectronics

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M27W400
Table 7. Read Mode DC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 2.7 to 3.6V; VPP = VCC)
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Maximum DC voltage on Output is VCC +0.5V.
Symbol
Parameter
Test Condition
Min
Max
Unit
ILI
Input Leakage Current
0V
≤ VIN ≤ VCC
±1
µA
ILO
Output Leakage Current
0V
≤ VOUT ≤ VCC
±10
µA
ICC
Supply Current
E = VIL, G = VIL,
IOUT = 0mA, f = 8MHz
20
mA
E = VIL, G = VIL,
IOUT = 0mA, f = 5MHz
15
mA
ICC1
Supply Current (Standby) TTL
E = VIH
1mA
ICC2
Supply Current (Standby) CMOS
E > VCC – 0.2V
15
µA
IPP
Program Current
VPP = VCC
10
µA
VIL
Input Low Voltage
–0.6
0.2 VCC
V
VIH
(2)
Input High Voltage
0.7 VCC
VCC + 0.5
V
VOL
Output Low Voltage
IOL = 2.1mA
0.4
V
VOH
Output High Voltage TTL
IOH = –400µA
2.4
V
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2-line con-
trol function which accommodates the use of mul-
tiple memory connection. The two-line control
function allows:
a. the lowest possible memory power dissipation
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
supplies to the devices. The supply current ICC
has three segments of importance to the system
designer: the standby current, the active current
and the transient peaks that are produced by the
falling and rising edges of E. The magnitude of the
transient current peaks is dependent on the ca-
pacitive and inductive loading of the device out-
puts. The associated transient voltage peaks can
be suppressed by complying with the two line out-
put control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
ic capacitor is used on every device between VCC
and VSS. This should be a high frequency type of
low inherent inductance and should be placed as
close as possible to the device. In addition, a
4.7µF electrolytic capacitor should be used be-
tween VCC and VSS for every eight devices. This
capacitor should be mounted near the power sup-
ply connection point. The purpose of this capacitor
is to overcome the voltage drop caused by the in-
ductive effects of PCB traces.


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