ICL7135C, TLC7135C

4 1/2DIGIT PRECISION

ANALOGTODIGITAL CONVERTERS

SLAS074D − DECEMBER 1986 − REVISED SEPTEMBER 2003

6

POST OFFICE BOX 655303

D1

D2

D3

D4

Deintegrate†

Signal Integrate

AUTO ZERO

D5†

Digit Scan

for OVER RANGE

STROBE

† First D5 of AUTO ZERO and deintegrate is one count longer.

Figure 4

PRINCIPLES OF OPERATION

A measurement cycle for the ICL7135C and TLC7135C consists of the following four phases.

1.

Auto-Zero Phase. The internal IN + and IN − inputs are disconnected from the terminals and internally

connected to ANLG COMMON. The reference capacitor is charged to the reference voltage. The

system is configured in a closed loop and the auto-zero capacitor is charged to compensate for offset

voltages in the buffer amplifier, integrator, and comparator. The auto-zero accuracy is limited only by the

system noise, and the overall offset, as referred to the input, is less than 10

µV.

2.

Signal Integrate Phase. The auto-zero loop is opened and the internal IN + and IN − inputs are

connected to the external terminals. The differential voltage between these inputs is integrated for a

fixed period of time. When the input signal has no return with respect to the converter power supply, IN−

can be tied to ANLG COMMON to establish the correct common-mode voltage. Upon completion of this

phase, the polarity of the input signal is recorded.

3.

Deintegrate Phase. The reference is used to perform the deintegrate task. The internal IN− is internally

connected to ANLG COMMON and IN+ is connected across the previously charged reference

capacitor. The recorded polarity of the input signal ensures that the capacitor is connected with the

correct polarity so that the integrator output polarity returns to zero. The time required for the output to

return to zero is proportional to the amplitude of the input signal. The return time is displayed as a digital

reading and is determined by the equation 10,000

4.

Zero Integrator Phase. The internal IN− is connected to ANLG COMMON. The system is configured in a

closed loop to cause the integrator output to return to zero. Typically, this phase requires 100 to 200

clock pulses. However, after an over-range conversion, 6200 pulses are required.