6.1.3
Power Control ........................................................................................................................... 60
6.1.4
Clock Control ............................................................................................................................ 60
6.1.5
System Control ......................................................................................................................... 62
6.2
Initialization and Configuration ................................................................................................... 63
6.3
Register Map ............................................................................................................................ 63
6.4
Register Descriptions ................................................................................................................ 64
7
Hibernation Module .......................................................................................................... 117
7.1
Block Diagram ........................................................................................................................ 118
7.2
Functional Description ............................................................................................................. 118
7.2.1
Register Access Timing ........................................................................................................... 118
7.2.2
Clock Source .......................................................................................................................... 119
7.2.3
Battery Management ............................................................................................................... 119
7.2.4
Real-Time Clock ...................................................................................................................... 119
7.2.5
Non-Volatile Memory ............................................................................................................... 120
7.2.6
Power Control ......................................................................................................................... 120
7.2.7
Interrupts and Status ............................................................................................................... 120
7.3
Initialization and Configuration ................................................................................................. 121
7.3.1
Initialization ............................................................................................................................. 121
7.3.2
RTC Match Functionality (No Hibernation) ................................................................................ 121
7.3.3
RTC Match/Wake-Up from Hibernation ..................................................................................... 121
7.3.4
External Wake-Up from Hibernation .......................................................................................... 122
7.3.5
RTC/External Wake-Up from Hibernation .................................................................................. 122
7.4
Register Map .......................................................................................................................... 122
7.5
Register Descriptions .............................................................................................................. 123
8
Internal Memory ............................................................................................................... 136
8.1
Block Diagram ........................................................................................................................ 136
8.2
Functional Description ............................................................................................................. 136
8.2.1
SRAM Memory ........................................................................................................................ 136
8.2.2
Flash Memory ......................................................................................................................... 137
8.3
Flash Memory Initialization and Configuration ........................................................................... 138
8.3.1
Flash Programming ................................................................................................................. 138
8.3.2
Nonvolatile Register Programming ........................................................................................... 139
8.4
Register Map .......................................................................................................................... 139
8.5
Flash Register Descriptions (Flash Control Offset) ..................................................................... 140
8.6
Flash Register Descriptions (System Control Offset) .................................................................. 147
9
General-Purpose Input/Outputs (GPIOs) ....................................................................... 160
9.1
Functional Description ............................................................................................................. 160
9.1.1
Data Control ........................................................................................................................... 160
9.1.2
Interrupt Control ...................................................................................................................... 161
9.1.3
Mode Control .......................................................................................................................... 162
9.1.4
Commit Control ....................................................................................................................... 162
9.1.5
Pad Control ............................................................................................................................. 162
9.1.6
Identification ........................................................................................................................... 163
9.2
Initialization and Configuration ................................................................................................. 163
9.3
Register Map .......................................................................................................................... 164
9.4
Register Descriptions .............................................................................................................. 166
September 02, 2007
4
Preliminary
Table of Contents