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LM3S1968-IRN50-B0T Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers

No. de pieza LM3S1968-IRN50-B0T
Descripción Electrónicos  Microcontroller
Download  525 Pages
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Fabricante Electrónico  ETC2 [List of Unclassifed Manufacturers]
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LM3S1968-IRN50-B0T Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers

  LM3S1968-IRN50-B0T Datasheet HTML 1Page - List of Unclassifed Manufacturers LM3S1968-IRN50-B0T Datasheet HTML 2Page - List of Unclassifed Manufacturers LM3S1968-IRN50-B0T Datasheet HTML 3Page - List of Unclassifed Manufacturers LM3S1968-IRN50-B0T Datasheet HTML 4Page - List of Unclassifed Manufacturers LM3S1968-IRN50-B0T Datasheet HTML 5Page - List of Unclassifed Manufacturers LM3S1968-IRN50-B0T Datasheet HTML 6Page - List of Unclassifed Manufacturers LM3S1968-IRN50-B0T Datasheet HTML 7Page - List of Unclassifed Manufacturers LM3S1968-IRN50-B0T Datasheet HTML 8Page - List of Unclassifed Manufacturers LM3S1968-IRN50-B0T Datasheet HTML 9Page - List of Unclassifed Manufacturers Next Button
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Table of Contents
About This Document .................................................................................................................... 19
Audience .............................................................................................................................................. 19
About This Manual ................................................................................................................................ 19
Related Documents ............................................................................................................................... 19
Documentation Conventions .................................................................................................................. 19
1
Architectural Overview ...................................................................................................... 21
1.1
Product Features ...................................................................................................................... 21
1.2
Target Applications .................................................................................................................... 27
1.3
High-Level Block Diagram ......................................................................................................... 27
1.4
Functional Overview .................................................................................................................. 28
1.4.1
ARM Cortex™-M3 ..................................................................................................................... 29
1.4.2
Motor Control Peripherals .......................................................................................................... 29
1.4.3
Analog Peripherals .................................................................................................................... 30
1.4.4
Serial Communications Peripherals ............................................................................................ 31
1.4.5
System Peripherals ................................................................................................................... 32
1.4.6
Memory Peripherals .................................................................................................................. 33
1.4.7
Additional Features ................................................................................................................... 33
1.4.8
Hardware Details ...................................................................................................................... 34
2
ARM Cortex-M3 Processor Core ...................................................................................... 35
2.1
Block Diagram .......................................................................................................................... 36
2.2
Functional Description ............................................................................................................... 36
2.2.1
Serial Wire and JTAG Debug ..................................................................................................... 36
2.2.2
Embedded Trace Macrocell (ETM) ............................................................................................. 37
2.2.3
Trace Port Interface Unit (TPIU) ................................................................................................. 37
2.2.4
ROM Table ............................................................................................................................... 37
2.2.5
Memory Protection Unit (MPU) ................................................................................................... 37
2.2.6
Nested Vectored Interrupt Controller (NVIC) ................................................................................ 37
3
Memory Map ....................................................................................................................... 41
4
Interrupts ............................................................................................................................ 43
5
JTAG Interface .................................................................................................................... 46
5.1
Block Diagram .......................................................................................................................... 47
5.2
Functional Description ............................................................................................................... 47
5.2.1
JTAG Interface Pins .................................................................................................................. 48
5.2.2
JTAG TAP Controller ................................................................................................................. 49
5.2.3
Shift Registers .......................................................................................................................... 50
5.2.4
Operational Considerations ........................................................................................................ 50
5.3
Initialization and Configuration ................................................................................................... 53
5.4
Register Descriptions ................................................................................................................ 53
5.4.1
Instruction Register (IR) ............................................................................................................. 53
5.4.2
Data Registers .......................................................................................................................... 55
6
System Control ................................................................................................................... 57
6.1
Functional Description ............................................................................................................... 57
6.1.1
Device Identification .................................................................................................................. 57
6.1.2
Reset Control ............................................................................................................................ 57
3
September 02, 2007
Preliminary
LM3S1968 Microcontroller


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