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M41T00M Datasheet(PDF) 6 Page - STMicroelectronics |
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M41T00M Datasheet(HTML) 6 Page - STMicroelectronics |
6 / 15 page M41T00 6/15 Table 9. Power Down/Up AC Characteristics (1) (TA = –40 to 85°C) Note: 1. VCC fall time should not exceed 5mV/µs. Symbol Parameter Min Max Unit tPD SCL and SDA at VIH before Power Down 0ns tREC SCL and SDA at VIH after Power Up 10 µs Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge relat- ed clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low dur- ing the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must sig- nal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave the data line High to enable the master to generate the STOP condition. Figure 5. Power Down/Up Mode AC Waveforms AI00596 VCC tREC tPD VSO SDA SCL DON'T CARE |
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