Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
TL16PC564BLVI Datasheet(PDF) 7 Page - Texas Instruments |
|
TL16PC564BLVI Datasheet(HTML) 7 Page - Texas Instruments |
7 / 34 page TL16PC564BLVI PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER SLLS627− SEPTEMBER 2004 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL INTER- † I/O DESCRIPTION NAME PZ NO. INTER- FACE† I/O DESCRIPTION WE 89 H I Write enable. WE is an active-low input signal used for strobing attribute-memory write data into the card. This signal has an internal pullup resistor WR(R/W) 31 S I Write or read/write enable. WR(R/W) is the active-low write enable in the Intel mode and read/write in the Zilog mode. XIN 42 M I Crystal input. XIN is a clock input divided internally based on the PGMCLK register value, then used as the primary UART clock input. VTEST 2 M I VTEST is an active-high production test input with an internal pulldown resistor. It can be left open or tied to ground. † Host = H, Subsystem = S, UART = U, Miscellaneous = M detailed description reset-validation circuit A reset-validation circuit has been implemented to qualify the active-high RESET input. At power up, the level on the RST output is unknown. Whenever RESET is stable for at least eight ARBCLKIs, RST reflects the inverted state of that stable value of RESET. Any changes on RESET must be valid for eight ARBCLKI clocks before the change is reflected on RST. This 8-clock filter provides needed hysteresis on the master reset input. RST is driven by a low-noise, open-drain, fail-safe output buffer. host CPU memory map The host CPU attribute memory space is mapped as follows: Host CPU Address Bits 9−1 (HA0 = 0) Attribute Memory Space 0 − 255 CIS 256 CCR0 257 CCR1 258 CCR2 259 CCR3 260 CCR4 261 CCR5 262 CCR6 263 CCR7 The host CPU I/O space is mapped as follows: Address Mode (hex) Normal Mode COM1 COM2 COM3 COM4 I/O Space 0 (DLAB = 0)† 3F8 2F8 3E8 2E8 UART receiver buffer register (RBR) − read only 0 (DLAB = 0)† 3F8 2F8 3E8 2E8 UART transmitter holding register (THR) − write only 0 (DLAB = 1)† 3F8 2F8 3E8 2E8 UART divisor latch LSB (DLL) 1 (DLAB = 0)† 3F9 2F9 3E9 2E9 UART interrupt enable register (IER) 1 (DLAB = 1)† 3F9 2F9 3E9 2E9 UART divisor latch MSB (DLM) 2 3F A 2F A 3EA 2EA UART interrupt identification register (IIR) − read only 2 3FA 2FA 3EA 2EA UART FIFO control register (FCR) − write only 3 3FB 2FB 3EB 2EB UART line control register (LCR) 4 3FC 2FC 3EC 2EC UART modem control register (MCR) − bit 5 read only 5 3FD 2FD 3ED 2ED UART line status register (LSR) 6 3FE 2FE 3EE 2EE UART modem status rgister (MSR) 7 3FF 2FF 3EF 2EF UART scratch register (SCR) † DLAB is bit 7 of the line control register (LCR). |
Número de pieza similar - TL16PC564BLVI |
|
Descripción similar - TL16PC564BLVI |
|
|
Enlace URL |
Política de Privacidad |
ALLDATASHEET.ES |
¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |