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SM320C40HFHM50 Datasheet(PDF) 8 Page - Texas Instruments |
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SM320C40HFHM50 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 64 page  SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS SGUS017H − OCTOBER 1993 − REVISED OCTOBER 2001 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 block diagram (continued) LD31 − LD0 LA30 − LA0 LDE LAE LSTAT3 − LSTAT0 LLOCK LSTRB0 − LSTRB1 LR/W0 − LR/W1 LPAGE0 − LPAGE1 LRDY0 − LRDY1 LCE0, LCE1 DMA Channel 0 DMA Channel 1 DMA Channel 2 DMA Channel 3 DMA Channel 4 DMA Channel 5 DMA Coprocessor Six DMA Channels 32 32 Global Local Port Control Global Control Register Time Period Register Timer 1 Timer Counter Register TCLK1 Global Control Register Time Period Register Timer 0 Timer Counter Register TCLK0 Port Control Registers Output FIFO Input FIFO PAU COM Port 0 CREQ0 CACK0 CSTRB0 CRDY0 C0D7−C0D0 P e r i p h e r a l D a t a B u s P e r i p h e r a l A d d r e s s B u s Port Control Registers Output FIFO Input FIFO PAU COM Port 5 CREQ5 CACK5 CSTRB5 CRDY5 C5D7−C5D0 MUX DDATA Bus DADDR 1 Bus DADDR 2 Bus DMADATA Bus PADDR Bus DMAADDR Bus PDATA Bus M U X 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 |
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