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ST10C167-Q3 Datasheet(PDF) 7 Page - STMicroelectronics |
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ST10C167-Q3 Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 63 page ST10R167 7/63 P2.0 - P2.7 P2.8 - P2.15 47 - 54 57 - 64 I/O 16-bit bidirectional I/O port, bit-wise programmable for input or output via direction bits. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 2 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special). The following Port 2 pins have alternate functions: 47 ... 54 57 ... 64 I/O ... I/O I/O I ... I/O I I P2.0 CC0IO CAPCOM: CC0 Capture Input/Compare Output ... ... ... P2.7 CC7IO CAPCOM: CC7 Capture Input/Compare Output P2.8 CC8IO CAPCOM: CC8 Capture Input/Compare Output EX0IN Fast External Interrupt 0 Input ... ... ... P2.15 CC15IO CAPCOM: CC15 Capture Input/Compare Output EX7IN Fast External Interrupt 7 Input T7IN CAPCOM2 Timer T7 Count Input P3.0 - P3.5 P3.6 - P3.13 P3.15 65 - 70 73 - 80 81 I/O I/O I/O 15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or output via direction bits. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 3 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins have alternate functions: 65 66 67 68 69 70 73 74 75 76 77 78 79 80 81 I O I O I I I I I/O I/O I/O O O I/O O P3.0 T0IN CAPCOM Timer T0 Count Input P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output P3.2 CAPIN GPT2 Register CAPREL Capture Input P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output P3.4 T3EUD GPT1 Timer T3 External Up/Down Control Input P3.5 T4IN GPT1 Timer T4 Input for Count/Gate/Reload/Capture P3.6 T3IN GPT1 Timer T3 Count/Gate Input P3.7 T2IN GPT1 Timer T2 Input for Count/Gate/Reload/Capture P3.8 MRST SSC Master-Receive/Slave-Transmit I/O P3.9 MTSR SSC Master-Transmit/Slave-Receive O/I P3.10 TxD0 ASC0 Clock/Data Output (Asynchronous/Synchronous) P3.11 RxD0 ASC0 Data Input (Asyn.) or I/O (Synchronous) P3.12 BHE External Memory High Byte Enable Signal, WRH External Memory High Byte Write Strobe P3.13 SCLK SSC Master Clock Output/Slave Clock Input P3.15 CLKOUT System Clock Output (=CPU Clock) P4.0 - P4.7 85 - 92 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bits. Programming an I/O pin as input forces the corresponding output driver to high impedance state. For external bus configuration, Port 4 can be used to output the segment address lines: 85 - 89 90 91 92 O O I O O O P4.0 - P4.4 A16 - A20 Least Significant Segment Address Line P4.5 A21 Segment Address Line CAN_RxD CAN Receive Data Input P4.6 A22 Segment Address Line, CAN_TxD CAN Transmit Data Output P4.7 A23 Most Significant Segment Address Line RD 95 O External Memory Read Strobe. RD is activated for every external instruc- tion or data read access. Table 1 : Pin list (continued) Symbol Pin Type Function II - PIN DATA (continued) |
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