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STK14EC8-BF15 Datasheet(PDF) 2 Page - Simtek Corporation |
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STK14EC8-BF15 Datasheet(HTML) 2 Page - Simtek Corporation |
2 / 19 page 2 Simtek Confidential Jan, 2008 Document Control #ML0060 Rev 1.1 STK14EC8 Preliminary PIN DESCRIPTIONS Pin Name I/O Description A18-A0 Input Address: The 19 address inputs select one of 524,288 bytes in the nvSRAM array DQ7-DQ0 I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM E Input Chip Enable: The active low E input selects the device W Input Write Enable Input, Active Low: When selected low, enables data on the IO pins to be written to the address location latched by the falling edge of CE. G Input Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high causes the DQ pins to tri-state. VCC Power Supply Power: 3.0V, +20%, -10% HSB I/O Hardware Store Busy: When low this output indicates a Store is in progress (also low during power up while busy). When pulled low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resis- tor keeps this pin high if not connected. (Connection Optional). VCAP Power Supply Autostore Capacitor: Supplies power to the nvSRAM during a power loss to store data from SRAM to nonvol- atile storage elements. VSS Power Supply Ground NC No Connect This pin is not connected to the die. (Do not connect in design; reserved for future use) 44-Pin TSOP-II VSS A0 A1 A2 A3 A4 A5 DQ0 DQ1 VCC VCAP DQ2 DQ3 A6 A7 A8 NC NC NC A18 A17 A16 A15 A14 A13 G DQ7 DQ6 VSS VCC DQ5 DQ4 HSB A12 A11 A9 NC NC NC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NC NC A10 W E (TOP) (See mechanical drawing on page 17) 48-Ball FBGA NC G A0 A1 A2 NC NC NC A3 A4 E NC DQ0 NC A5 A6 NC DQ4 VSS DQ1 A17 A7 DQ5 VCC VCC DQ2 VCAP A16 DQ6 VSS DQ3 NC A14 A15 NC DQ7 NC HSB A12 A13 W NC A18 A8 A9 A10 A11 NC 1 2 3 4 5 6 B C D E F G H (TOP) A (See mechanical drawing on page 18) |
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