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ST486DX Datasheet(PDF) 11 Page - STMicroelectronics |
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ST486DX Datasheet(HTML) 11 Page - STMicroelectronics |
11 / 34 page Instruction Opcode Parameters Core Clocks RSM 0F AA None 76 Instruction Opcode Parameters Core Clocks RSTS 0F 7D [mod 000 r/m] mem80 10 Instruction Opcode Parameters Core Clocks SMINT 0F 7E None 24 Instruction Opcode Parameters Core Clocks RSLDT 0F 7B[mod 000 r/m] mem80 10 2.3.2 RSLDT - Restore LDT and Descriptor ST486DX - SMM IMPLEMENTATION 19 RSLDT loads the information at the mem80 into Local Descriptor Table Register and its associated descriptor. 2.3.3 RSM - Resume Back to Normal Mode RSM will restore the state of the CPU from the SMM header at the top of SMM space and exit SMM. This is the last instruction executed in an SMI handler. After the CPU state is restored, the SMI# pin is driven inactive for one clock then floated so the pin can be driven by the system. 2.3.4 RSTS - Restore TSR and Descriptor RSTS loads the information at the mem80 address into the Task Register and its associated descriptor. 2.3.5 SMINT - Software SMM Interrupt SMINT will cause the CPU to enter SMM as though the hardware SMI# pin was sampled low. The S bit in the SMM header is set. The SMI# signal is not driven by the CPU when SMM is en- tered with SMINT. |
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