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ST6373 Datasheet(PDF) 4 Page - STMicroelectronics |
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ST6373 Datasheet(HTML) 4 Page - STMicroelectronics |
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4 / 64 page  ST6373 4/64 1 GENERAL DESCRIPTION 1.1 INTRODUCTION ST6373 Microcontrollers are members of the 8-bit HCMOS ST637x family, a series of devices spe- cially intended for Digitally Controlled Multi Fre- quency Monitor applications. All ST637x devices are based on a building block approach: a com- mon core is surrounded by a combination of on- chip peripherals (macrocells) available from a standard library. ST6373 devices are available in functionally iden- tical ROM, OTP (ST63T73) and EPROM (ST63E73) versions, all with the same pinout. ROM devices are available with 8, 12 or 16K Pro- gram memory, whereas OTP and EPROM ver- sions are both available in 16K versions only. For details relating to sales types, refer to Section 7.2. Since ROM, OTP and EPROM versions are functionally identical, the present Datasheet will refer to the generic ST6373 device, except where specific versions differ in detail. The ST6373 devices feature: – Nine PWM outputs, which can be used as Digital to Analog converter outputs (with external RC fil- ters). These are suitable for tuning and other functions. – A PWM output with Bit Rate Multiplier, to which the above comments apply. – An Event Counter especially designed to calcu- late the HSYNC (or HDRIV) Frequency, using one of the on-chip timers. – A Period Counter especially designed to calcu- late the VSYNC Period. – A Polarity Detector for HSYNC (or HDRIV) and VSYNC. – HSYNC and VSYNC outputs with controlled po- larity. – Video Blanking and Clamping Outputs. – Two I/O ports A & B usable for a keyboard wake- up feature since an interrupt input ored on each of their pins. – An Analog to Digital converter connected to port B which can be used to decode an analog key- board or for AFC. – A VSYNC input pin connected to an interrupt vector and to the DDC SPI for DDC1 protocol. – An NMI input which can be used, for example, as a Remote Control input for a TV application. – A hardware DDC SPI able to manage DDC1 (VSYNC as clock), DDC2B and DDC2AB (I 2C BUS Multimaster and Slave). A 128-byte dedicated EEPROM memory is available for DDC1 and DDC2B. – Hardware I 2C SPI for internal monitor bus and to manage, for example, an OSD. – A Mirror Register and a XOR Register are includ- ed to complement the basic ST6 instruction set. Table 1. ST6373 Device Summary Note: See Ordering Information in Table 23 at the end of the Datasheet. DEVICE CONFIGURATION Program Memory (Bytes) RAM (Bytes) EEPROM (Bytes) A/D Inputs 14-bit D/ (PWM) Output 7-bit D/A (PWM) Output EMULATING DEVICES ST6373 8K ROM 12K ROM 16K ROM 192 512 8 1 9 ST63E73,ST63T73 ST63T73 16K OTP 192 512 8 1 9 - ST63E73 16K EPROM 192 512 8 1 9 - |
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