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ST662ABN Datasheet(PDF) 6 Page - STMicroelectronics |
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ST662ABN Datasheet(HTML) 6 Page - STMicroelectronics |
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6 / 12 page  APPLICATION CIRCUIT Based on fast charge/discharge of capacitors, this circuit involves high di/dt values limited only by Ron of switches. This implies a critical layout design due to the need to minimize inductive paths and place capacitors as close as possible to the device. A good layout design is strongly recommended for noise reason. For best performance, use very short connections to the capacitors and the values shown in table 1. C3 and C4 must have low ESR in order to minimize the output ripple. Their values can be reduced to 2 µF and 1µF, respectively, when using ceramic capacitors, but must be of 10 µFor larger if aluminium electrolytic are chosen. C5 must be placed as close to the device as possible and could be omitted if very low output noise performance are not required. Fig 4 and Fig 5 show, respectively, our EVALUATION kit layout and the relatively electrical shematic. Table 1: List of Components CAPACITOR TYPE VALUE ( µF) Charge Pump C1 Ceramic 0.22 Charge Pump C2 Ceramic 0.22 Input C3 Electrolyt ic Tant alum 4. 7 O utput C4 Electrolyt ic Tant alum 4. 7 Decoupling C5 Ceramic 0. 1 Figure 5: Electrical Schematic Figure 4: KIT Lay-out ST662A 6/12 |
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