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TPS40132RHBT Datasheet(PDF) 8 Page - Texas Instruments |
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TPS40132RHBT Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 40 page  www.ti.com TPS40132 SLUS776A – DECEMBER 2007 – REVISED FEBRUARY 2008 Terminal Functions (continued) TERMINAL I/O DESCRIPTION NAME NO. Gate drive output for the high-side N-channel MOSFET switch for PWM2. Output is referenced to SW2 and HDRV2 25 O is bootstrapped for enhancement of the high-side switch Used to set the cycle-by-cycle current limit threshold. If ILIM threshold is reached, the PWM cycle is terminated and the converter delivers limited current to the output. The relationship between ILIM and the ILIM 15 I maximum phase current is described in Equation 2 and Equation 3. See the Overcurrent Protection section for more details. Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET for PWM1. See Layout LDRV1 29 O Considerations section. Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET for PWM2. See Layout LDRV2 27 O Considerations section. OVSET 2 I A resistor divider, on this pin connected to the output voltage sets the overvoltage sense point. Power good indicator of the output voltage. This open-drain output connects to a voltage via an external PGOOD 16 O resistor. When the FB pin voltage is between 93% and 107% of VREF, the PGOOD output is in a high impedance state. Power ground reference for the controller lower gate drivers. There should be a high-current return path PGND 28 - from the sources of the lower MOSFETs to this pin. RT 17 I Connecting a resistor from this pin to ground sets the oscillator frequency. Provides user programmable soft-start by means of a capacitor connected to the pin. If an undervoltage or SS 23 I over current fault is detected the soft-start capacitor cycles 7 times with no switching before a normal soft-start sequence allowed. Connect to the switched node on converter 1. Power return for the channel 1 upper gate driver. There SW1 31 I should be a high-current return path from the source of the upper MOSFET to this pin. It is also used by the adaptive gate drive circuits to minimize the dead time between upper and lower MOSFET conduction. Connect to the switched node on converter 2. Power return for the channel 2 upper gate driver. There SW2 26 I should be a high-current return path from the source of the upper MOSFET to this pin. It is also used by the adaptive gate drive circuits to minimize the dead time between upper and lower MOSFET conduction. UVLO 22 O A voltage divider from VIN to this pin, set to 1V, determines the input voltage that starts the controller. Power input for the LDO linear regulator that powers the differential amplifier and the current sense VDD 12 I amplifiers. VOUT 3 I Non-inverting input of the differential amplifier. This pin should be connected to VOUT at the point of load. VREF 9 O Output of an internal reference voltage. The load may be up to 100- µA DC. VIN5 30 I Power input for the device. A 1.0- µF ceramic capacitor should be connected from this pin to ground. 8 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :TPS40132 |
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