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TPS40211DGQR Datasheet(PDF) 10 Page - Texas Instruments |
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TPS40211DGQR Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 46 page  DEVICE INFORMATION 1 6 5 10 2 3 7 4 8 9 FB RC COMP DIS/EN SS GND VDD ISNS GDRV BP DGQ PowerPAD PACKAGE (Top View) FB RC COMP DIS/EN SS 5 4 3 2 1 1 6 7 8 9 10 GND VDD ISNS GDRV BP DRC SURFACE MOUNT PACKAGE (Top View) TPS40210, TPS40211 SLUS772B – MARCH 2008 – REVISED JUNE 2008.......................................................................................................................................................... www.ti.com TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. COMP 4 O Error amplifier output. Connect control loop compensation network between COMP pin and FB pin. Disable pin. Pulling this pin high, places the part into a shutdown mode. Shutdown mode is characterized by a very low quiescent current. While in shutdown mode, the functionality of all blocks is disabled and the BP DIS/EN 3 I regulator is shut down. This pin has an internal 1-M Ω pull-down resistor to GND. Leaving this pin unconnected enables the device. Error amplifier inverting input. Connect a voltage divider from the output to this pin to set output voltage. FB 5 I Compensation network is connected between this pin and COMP. GDRV 8 O Connect the gate of the power N channel MOSFET to this pin. GND 6 - Device ground. Current sense pin. Connect an external current sensing resistor between this pin and GND. The voltage on this pin is used to provide current feedback in the control loop and detect an overcurrent condition. An ISNS 7 I overcurrent condition is declared when ISNS pin voltage exceeds the overcurrent threshold voltage, 150 mV typical. Switching frequency setting pin. Connect capacitor from RC pin to GND. Connect a resistor from RC pin RC 1 I toVDD of the IC power supply and a capacitor from RC to GND. Soft-start time programming pin. Connect capacitor from SS pin to GND to program converter soft-start time. SS 2 I This pin also functions as a timeout timer when the power supply is in an overcurrent condition. BP 9 O Regulator output pin. Connect a 1.0- µF bypass capacitor from this pin to GND. System input voltage. Connect a local bypass capacitor from this pin to GND. Depending on the amount of VDD 10 I required slope compensation, this pin can be connected to the converter output. See Application Information section for additional details. DGQ PowerPAD PACKAGE DRC PACKAGE (TOP VIEW) (TOP VIEW) 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPS40210 TPS40211 |
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