LM3S316 Data Sheet
October 8, 2006
9
Preliminary
Figure 14-10. Master Burst RECEIVE ........................................................................................................... 308
Figure 14-11. Master Burst RECEIVE after Burst SEND...............................................................................309
Figure 14-12. Master Burst SEND after Burst RECEIVE...............................................................................309
Figure 14-13. Slave Command Sequence..................................................................................................... 310
Figure 15-1.
Analog Comparator Module Block Diagram ............................................................................ 334
Figure 15-2.
Structure of Comparator Unit................................................................................................... 335
Figure 15-3.
Comparator Internal Reference Structure ............................................................................... 336
Figure 16-1.
PWM Module Block Diagram................................................................................................... 345
Figure 16-2.
PWM Count-Down Mode......................................................................................................... 346
Figure 16-3.
PWM Count-Up/Down Mode ................................................................................................... 347
Figure 16-4.
PWM Generation Example In Count-Up/Down Mode ............................................................. 347
Figure 16-5.
PWM Dead-Band Generator ................................................................................................... 348
Figure 17-1.
Pin Connection Diagram.......................................................................................................... 377
Figure 20-1.
Load Conditions....................................................................................................................... 392
Figure 20-2.
I2C Timing................................................................................................................................ 395
Figure 20-3.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement ................ 396
Figure 20-4.
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer................................. 397
Figure 20-5.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1...................................................... 397
Figure 20-6.
JTAG Test Clock Input Timing................................................................................................. 399
Figure 20-7.
JTAG Test Access Port (TAP) Timing ..................................................................................... 399
Figure 20-8.
JTAG TRST Timing ................................................................................................................. 399
Figure 20-9.
External Reset Timing (RST)................................................................................................... 401
Figure 20-10. Power-On Reset Timing .......................................................................................................... 401
Figure 20-11. Brown-Out Reset Timing ......................................................................................................... 401
Figure 20-12. Software Reset Timing ............................................................................................................ 401
Figure 20-13. Watchdog Reset Timing .......................................................................................................... 402
Figure 20-14. LDO Reset Timing ................................................................................................................... 402
Figure 21-1.
48-Pin LQFP Package............................................................................................................. 403
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