Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
M41T00S Datasheet(PDF) 7 Page - STMicroelectronics |
|
M41T00S Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 26 page M41T00S Operation 7/26 2 Operation The M41T00S clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 8 bytes contained in the device can then be accessed sequentially in the following order: 1. Seconds register 2. Minutes register 3. Century/hours register 4. Day register 5. Date register 6. Month register 7. Year register 8. Calibration register The M41T00S clock continually monitors VCC for an out-of-tolerance condition. Should VCC fall below VPFD, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. Once VCC falls below the switchover voltage (VSO), the device automatically switches over to the battery and powers down into an ultra-low current mode of operation to preserve battery life. If VBAT is less than VPFD, the device power is switched from VCC to VBAT when VCC drops below VBAT. If VBAT is greater than VPFD, the device power is switched from VCC to VBAT when VCC drops below VPFD. Upon power-up, the device switches from battery to VCC at VSO. When VCC rises above VPFD, it will recognize the inputs. For more information on battery storage life refer to Application Note AN1012. 2.1 2-wire bus characteristics The bus is intended for communication between different ICs. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined: ● Data transfer may be initiated only when the bus is not busy. ● During data transfer, the data line must remain stable whenever the clock line is high. ● Changes in the data line, while the clock line is high, will be interpreted as control signals. Accordingly, the following bus conditions have been defined: 2.1.1 Bus not busy Both data and clock lines remain high. 2.1.2 Start data transfer A change in the state of the data line, from high to low, while the clock is high, defines the START condition. |
Número de pieza similar - M41T00S |
|
Descripción similar - M41T00S |
|
|
Enlace URL |
Política de Privacidad |
ALLDATASHEET.ES |
¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |