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LFTVS18-1F3 Datasheet(PDF) 5 Page - STMicroelectronics |
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LFTVS18-1F3 Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 7 page LFTVS18-1F3 Package information 5/7 3 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 14. Flip chip dimensions Figure 15. Footprint recommendations Figure 16. Marking 185 µm ± 10 0.77 mm ± 30 µm 255 µm ± 40 205 µm ± 40 400 µm ± 40 605 µm ± 55 220 µm recommended 220 µm recommended 260 µm maximum Solder stencil opening: Copper pad Diameter: Solder mask opening: 300 µm minimum x y x w z w Dot xx = marking yww = datecode (y = year ww = week) z = manufacturing location |
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