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LC4128ZE5TN100IES Datasheet(PDF) 1 Page - Lattice Semiconductor |
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LC4128ZE5TN100IES Datasheet(HTML) 1 Page - Lattice Semiconductor |
1 / 54 page www.latticesemi.com 1 DS1022_01.2 ispMACH 4000ZE Family 1.8V In-System Programmable Ultra Low Power PLDs August 2008 Data Sheet DS1022 ® © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Features ■ High Performance •fMAX = 260MHz maximum operating frequency •tPD = 4.4ns propagation delay • Up to four global clock pins with programmable clock polarity control • Up to 80 PTs per output ■ Ease of Design • Flexible CPLD macrocells with individual clock, reset, preset and clock enable controls • Up to four global OE controls • Individual local OE control per I/O pin • Excellent First-Time-Fit TM and refit • Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders ■ Ultra Low Power • Standby current as low as 10µA typical • 1.8V core; low dynamic power • Operational down to 1.6V VCC • Superior solution for power sensitive consumer applications • Per pin pull-up, pull-down or bus keeper control* • Power Guard with multiple enable signals* ■ Broad Device Offering • 32 to 256 macrocells • Multiple temperature range support – Commercial: 0 to 90°C junction (Tj) – Industrial: -40 to 105°C junction (Tj) • Space-saving packages ■ Easy System Integration • Operation with 3.3V, 2.5V, 1.8V or 1.5V LVCMOS I/O • 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces • Hot-socketing support • Open-drain output option • Programmable output slew rate • 3.3V PCI compatible • I/O pins with fast setup path • Input hysteresis* • 1.8V core power supply • IEEE 1149.1 boundary scan testable • IEEE 1532 ISC compliant • 1.8V In-System Programmable (ISP™) using Boundary Scan Test Access Port (TAP) • Pb-free package options (only) • On-chip user oscillator and timer* *New enhanced features over original ispMACH 4000Z Table 1. ispMACH 4000ZE Family Selection Guide ispMACH 4032ZE ispMACH 4064ZE ispMACH 4128ZE ispMACH 4256ZE Macrocells 32 64 128 256 tPD (ns) 4.4 4.7 5.8 5.8 tS (ns) 2.2 2.5 2.9 2.9 tCO (ns) 3.0 3.2 3.8 3.8 fMAX (MHz) 260 241 200 200 Supply Voltages (V) 1.8V 1.8V 1.8V 1.8V Packages 1 (I/O + Dedicated Inputs) 48-Pin TQFP (7 x 7mm) 32+4 32+4 64-Ball csBGA (5 x 5mm) 32+4 48+4 100-Pin TQFP (14 x 14mm) 64+10 64+10 64+10 144-Pin TQFP (20 x 20mm) 96+4 96+14 144-Ball csBGA (7 x 7mm) 64+10 96+4 108+4 1. Pb-free only. |
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