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ST72C334J2TA Datasheet(PDF) 7 Page - STMicroelectronics |
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ST72C334J2TA Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 150 page ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 7/150 1 PREAMBLE: ST72C334-Auto VERSUS ST72E331 SPECIFICATION New Features available on the ST72C334-Auto ■ 8 or 16K Flash/ROM with In-Situ Programming and Readout protection ■ New ADC with a better accuracy and conversion time ■ New configurable Clock, Reset and Supply system ■ New power saving mode with real-time base: Active Halt ■ Beep capability on PF1 ■ New interrupt source: Clock security system (CSS) or Main clock controller (MCC) ST72C334-Auto I/O Configuration and Pinout ■ Same pinout as ST72E331 ■ PA6 and PA7 are true open drain I/O ports without pull-up (same as ST72E331) ■ PA3, PB3, PB4 and PF2 have no pull-up configuration (all I/Os present on TQFP44) ■ PA5:4, PC3:2, PE7:4 and PF7:6 have high sink capabilities (20mA on N-buffer, 2mA on P-buffer and pull-up). On the ST72E331, all these pads (except PA5:4) were 2mA push-pull pads without high sink capabilities. PA4 and PA5 were 20mA true open drains. New Memory Locations in ST72C334-Auto ■ 20h: MISCR register becomes MISCR1 register (naming change) ■ 29h: new control/status register for the MCC module ■ 2Bh: new control/status register for the Clock, Reset and Supply control. This register replaces the WDGSR register keeping the WDOGF flag compatibility. ■ 40h: new MISCR2 register |
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