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LFXP10E-3F256C Datasheet(PDF) 7 Page - Lattice Semiconductor |
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LFXP10E-3F256C Datasheet(HTML) 7 Page - Lattice Semiconductor |
7 / 130 page 2-4 Architecture Lattice Semiconductor LatticeXP Family Data Sheet Table 2-1. Slice Signal Descriptions Modes of Operation Each Slice is capable of four modes of operation: Logic, Ripple, RAM and ROM. The Slice in the PFF is capable of all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks. Table 2-2. Slice Modes Logic Mode: In this mode, the LUTs in each Slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any logic function with four inputs can be generated by programming this lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger lookup tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other Slices. Ripple Mode: Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the fol- lowing functions can be implemented by each Slice: • Addition 2-bit • Subtraction 2-bit • Add/Subtract 2-bit using dynamic control • Up counter 2-bit • Down counter 2-bit • Ripple mode multiplier building block • Comparator functions of A and B inputs - A greater-than-or-equal-to B - A not-equal-to B - A less-than-or-equal-to B Two additional signals: Carry Generate and Carry Propagate are generated per Slice in this mode, allowing fast arithmetic functions to be constructed by concatenating Slices. RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x1-bit memory. Through the combination of LUTs and Slices, a variety of different memories can be constructed. Function Type Signal Names Description Input Data signal A0, B0, C0, D0 Inputs to LUT4 Input Data signal A1, B1, C1, D1 Inputs to LUT4 Input Multi-purpose M0 Multipurpose Input Input Multi-purpose M1 Multipurpose Input Input Control signal CE Clock Enable Input Control signal LSR Local Set/Reset Input Control signal CLK System Clock Input Inter-PFU signal FCIN Fast Carry In 1 Output Data signals F0, F1 LUT4 output register bypass signals Output Data signals Q0, Q1 Register Outputs Output Data signals OFX0 Output of a LUT5 MUX Output Data signals OFX1 Output of a LUT6, LUT7, LUT8 2 MUX depending on the slice Output Inter-PFU signal FCO For the right most PFU the fast carry chain output 1 1. See Figure 2-2 for connection details. 2. Requires two PFUs. Logic Ripple RAM ROM PFU Slice LUT 4x2 or LUT 5x1 2-bit Arithmetic Unit SP 16x2 ROM 16x1 x 2 PFF Slice LUT 4x2 or LUT 5x1 2-bit Arithmetic Unit N/A ROM 16x1 x 2 |
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