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LFE220E-5F484I Datasheet(PDF) 5 Page - Lattice Semiconductor |
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LFE220E-5F484I Datasheet(HTML) 5 Page - Lattice Semiconductor |
5 / 386 page 2-2 Architecture Lattice Semiconductor LatticeECP2/M Family Data Sheet Figure 2-1. Simplified Block Diagram, ECP2-6 Device (Top Level) Figure 2-2. Simplified Block Diagram, ECP2M20 Device (Top Level) Programmable Function Units (PFUs) Flexible sysIO Buffers: LVCMOS, HSTL, SSTL, LVDS, and other standards sysDSP Blocks Multiply and Accumulate Support sysMEM Block RAM 18kbit Dual Port sysCLOCK PLLs and DLLs Frequency Synthesis and Clock Alignment Flexible routing optimized for speed, cost and routability Configuration logic, including dual boot and encryption. On-chip oscillator and soft-error detection. Configuration port Pre-engineered source synchronous support • DDR1/2 • SPI4.2 • ADC/DAC devices Flexible sysIO Buffers: LVCMOS, HSTL SSTL, LVDS Pre-Engineered Source Synchronous Support • DDR1/2 • SPI4.2 • ADC/DAC devices SERDES DSP Blocks Multiply & Accumulate Support On-Chip Oscillator Programmable Function Units (PFUs) Channel 3 Channel 2 Channel 1 Channel 0 sysMEM Block RAM 18kbit Dual Port Configuration Logic, Including dual boot and encryption, and soft-error detection Flexible Routing optimized for speed, cost & routability sysCLOCK GPLLs & GDLLs Frequency Synthesis & Clock Alignment Configuration Port sysCLOCK SPLLs |
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