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STPD0166BTI3 Datasheet(PDF) 3 Page - STMicroelectronics |
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STPD0166BTI3 Datasheet(HTML) 3 Page - STMicroelectronics |
3 / 48 page STPC CLIENT Issue 1.7 - February 8, 2000 3/48 • ISA master/slave • The ISA clock generated from either 14.318MHz oscillator clock or PCI clock • Supports programmable extra wait state for ISA cycles • Supports I/O recovery time for back to back I/ O cycles. • Fast Gate A20 and Fast reset. • Supports the single ROM that C, D, or E. blocks shares with F block BIOS ROM. • Supports flash ROM. • Buffered DMA & ISA master cycles to reduce bandwidth utilization of the PCI and Host bus. • IDE Interface • Supports PIO • Supports up to Mode 5 Timings • Supports up to 4 IDE devices • Individual drive timing for all four IDE devices • Concurrent channel operation (PIO modes) - 4 x 32-Bit Buffer FIFO per channel • Support for PIO mode 3 & 4 • Support for 11.1/16.6 MB/s, I/O Channel Ready PIO data transfers. • Supports both legacy & native IDE modes • Supports hard drives larger than 528MB • Support for CD-ROM and tape peripherals • Backward compatibility with IDE (ATA-1). • Integrated peripheral controller • 2X8237/AT compatible 7-channel DMA con- troller. • 2X8259/AT compatible interrupt Controller. 16 interrupt inputs - ISA and PCI. • Three 8254 compatible Timer/Counters. • Power Management • Four power saving modes: On, Doze, Stand- by, Suspend. • Programmable system activity detector • Supports SMM. • Supports STOPCLK. • Supports IO trap & restart. • Independent peripheral time-out timer to monitor hard disk, serial & parallel ports. • Supports RTC, interrupts and DMAs wake-up |
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