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FIN12ACGFX Datasheet(PDF) 3 Page - Fairchild Semiconductor |
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FIN12ACGFX Datasheet(HTML) 3 Page - Fairchild Semiconductor |
3 / 21 page © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.2 3 Terminal Descriptions Note: 1 The DSO/DSI serial port pins have been arranged such that if one device is rotated 180° with respect to the other device, the serial connections properly aligns without the need for any traces or cable signals to cross. Other layout orientations may require that traces or cables cross. Pin Name I/O Type Number of Terminals Description of Signals DP[1:12] I/O 12 LVCMOS parallel I/O, Direction controlled by DIRI pin CKREF IN 1 LVCMOS clock input and PLL reference STROBE IN 1 LVCMOS strobe signal for latching data into the serializer CKP OUT 1 LVCMOS word clock output. This signal is the regenerated STROBE signal DSO+ / DSI- DSO- / DSI+ DIFF-I/O 2 CTL differential serial I/O data signals(1) DSO: Refers to output signal pair DSI: Refers to input signal pair DSO(I)+: Positive signal of DSO(I) pair DSO(I)-: Negative signal of DSO(I) pair CKSI+ / CKSI- DIFF-IN 2 CTL differential deserializer input bit clock CKSI: Refers to signal pair CKSI+: Positive signal of CKSI pair CKSI-: Negative signal of CKSI pair CKSO+ / CKSO- DIFF-OUT 2 CTL differential deserializer output bit clock CKSO: Refers to signal pair CKSO+: Positive signal of CKSO pair CKSO-: Negative signal of CKSO pair S1 IN 1 Used to define frequency range for the RefClock, CKREF. S2 IN 1 PLLx_SEL IN 1 Used to define PLL multiplication mode. PLLX_SEL = 0 multiplication factor 7-1/3x PLLX_SEL = 1 multiplication factor 7x DIRI IN 1 LVCMOS control input. Used to control direction of data flow: DIRI = “1” Serializer DIRI = “0” Deserializer DIRO OUT 1 LVCMOS output, inversion of DIRI VDDP Supply 1 Power supply for parallel I/O and translation circuitry VDDS Supply 1 Power supply for core and serial I/O VDDA Supply 1 Power supply for analog PLL circuitry GND Supply 0 Use bottom ground plane for ground signals |
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