LC87F2932A

No.A1210-4/29

Oscillation Circuits

• RC oscillation circuit (internal):

For system clock

• CF oscillation circuit:

For system clock, with internal Rf

• Crystal oscillation circuit:

For low-speed system clock, with internal Rf

• Frequency variable RC oscillation circuit (internal): For system clock

1) Adjustable in ±4% (typ) step from a selected center frequency.

2) Measures oscillation clock using a input signal from XT1 as a reference.

System Clock Divider Function

• Can run on low current.

• The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs,

and 76.8

μs (at a main clock rate of 10MHz).

Standby Function

• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.

1) Oscillation is not halted automatically.

2) There are three ways of resetting the HALT mode.

(1) Setting the reset pin to the low level

(2) System resetting by watchdog timer

(3) Occurrence of an interrupt

• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.

1) The CF, RC, X’tal, and frequency variable RC oscillators automatically stop operation.

2) There are four ways of resetting the HOLD mode.

(1) Setting the reset pin to the low level.

(2) System resetting by watchdog timer

(3) Having an interrupt source established at either INT0, INT1, INT2, INT4, INT5, INT6, or INT7

* INT0 and INT1 HOLD mode reset is available only when level detection is set.

(4) Having an interrupt source established at port 0

• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.

1) The CF, RC, and frequency variable RC oscillators automatically stop operation.

2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.

3) There are six ways of resetting the X'tal HOLD mode.

(1) Setting the reset pin to the low level

(2) System resetting by watchdog timer

(3) Having an interrupt source established at either INT0, INT1, INT2, INT4, INT5, INT6, or INT7

* INT0 and INT1 HOLD mode reset is available only when level detection is set.

(4) Having an interrupt source established at port 0

(5) Having an interrupt source established in the base timer circuit

(6) Having an interrupt source established in the day and time counter circuit

On-chip Debugger

• Supports software debugging with the IC mounted on the target board (LC87D2932A).

LC87F2932A has an On-chip debugger but its function is limited.

Package Form

• QIP64E (14 × 14):

Lead-free type

• TQFP64J (7 × 7):

Lead-free type

• FLGA68K (6.0 × 6.0): Lead-free type

• FLGA64 (5.0 × 5.0):

Lead-free type

Development Tools

• On-chip debugger: TCB87- TypeB + LC87D2932A