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LC890561W Datasheet(PDF) 11 Page - Sanyo Semicon Device |
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LC890561W Datasheet(HTML) 11 Page - Sanyo Semicon Device |
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11 / 47 page  LC890561W No8226-11/47 9. Built-in Regulator (VREF) • It has built-in regulator that can step down 3.3V to 1.8V in order to supply voltage into logic part. • VREF is pin for voltage smoothing which can output regulator and connects the capacity as shown below. C0 C1 10 µF 0.1 µF Figure 9.1 Composition of the regulator output 10. Analog Source Mode • The analog source mode is entered under the following conditions. −When the analog source mode is selected with the SMOD command. −When the input pin selected for data demodulation is no signal. • In the analog source mode, the oscillation amplifier clock or the externally supplied clock are used. • Each signal in the analog source mode is described below. −VCO holds the status of free-run oscillation when SMOD is set and also when no signal is input. −ERROR pin outputs high and DATAO pin outputs SDIN input data. −XSTATE pin outputs high after about 512*LRCK(fs) (LRCK=48kHz or 96kHz) counts after XSTATE pin outputs low. −The clock set with XADC command is output from XMCK. −The output of BCK and LRCK are as follows. Table 10.1 BCK and LRCK Outputs with Analog Source XIN pin BCK pin LRCK pin 12.288MHz 3.072MHz 48kHz 24.576MHz 6.144MHz 96kHz 12MHz to 25MHz XIN/4 XIN/256 VREF C0 C1 |
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