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AD5065BRUZ-REEL7 Datasheet(PDF) 8 Page - Analog Devices |
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AD5065BRUZ-REEL7 Datasheet(HTML) 8 Page - Analog Devices |
8 / 28 page AD5025/AD5045/AD5065 Rev. 0 | Page 8 of 28 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 AD5025/ AD5045/ AD5065 VDD VREFA SDO POR VOUTA 14 13 12 11 10 9 8 DIN GND VOUTB SCLK TOP VIEW (Not to Scale) LDAC CLR PDL SYNC VREFB Figure 5. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. This pin can be tied permanently low in standalone mode. When daisy-chain mode is enabled, this pin cannot be tied permanently low. The LDAC pin should be used in asynchronous LDAC update mode, as shown in Figure 3, and the LDAC pin must be brought high after pulsing. This allows all DAC outputs to simultaneously update. 2 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input register. Data is transferred in on the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. 3 VDD Power Supply Input. These parts can be operated from 4.5 V to 5.5 V, and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 4 VREFA DAC A Reference Input. This is the reference voltage input pin for DAC A. 5 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 6 POR Power-On Reset Pin. Tying this pin to GND powers up the part to 0 V. Tying this pin to VDD powers up the part to midscale. 7 SDO Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. 8 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are updated with the data contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V. 9 VREFB DAC B Reference Input. This is the reference voltage input pin for DAC B. 10 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 11 GND Ground Reference Point for All Circuitry on the Part. 12 PDL The PDL pin is used to ensure hardware shutdown lockout of the device under any circumstance. A Logic 1 at the PLO pin causes the device to behave as normal. The user may successfully enter software power-down over the serial interface while Logic 1 is applied to the PDL pin. If a Logic 0 is applied to this pin, it ensures that the device cannot enter software power-down under any circumstances. If the device had previously been placed in software power-down mode, a high-to- low transition at the PDL pin causes the DAC(s) to exit power-down and output a voltage corresponding to the previous code in the DAC register before the device entered software power-down. 13 DIN Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 14 SCLK Serial Clock Input. Data is clocked into the input register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. |
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