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ADF9010BCPZ-RL7 Datasheet(PDF) 9 Page - Analog Devices |
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ADF9010BCPZ-RL7 Datasheet(HTML) 9 Page - Analog Devices |
9 / 28 page ADF9010 Rev. 0 | Page 9 of 28 Pin No. Mnemonic Description 17 VTUNE Control Input to the VCO. This input determines the VCO frequency and is derived from filtering the CP output. 19, 20 LOEXTP, LOEXTN Single-Ended External VCO Input of 50 Ω. This is used if the ADF9010 utilizes an optional external VCO. These pins are internally dc-biased and must be ac-coupled. AC-couple LOEXTN to ground with 100 pF and ac-couple the VCO signal with 100 pF through LOEXTP. 22, 23 TxOUTP, TxOUTN Buffered Tx Output. These pins contain the Tx output signal, which can be combined in a balun for best results. 25, 26 TxBBQN, TxBBQP Baseband Quadrature Phase Input/Complementary Input to the Transmit Modulator. 27, 28 TxBBIP, TxBBIN Baseband In-Phase Input/Complementary to the Transmit Modulator. 30 RSET Connecting a resistor between this pin and AGND sets the maximum charge pump output current. The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is ICPMAX = 25.5/RSET where: RSET is 5.1 kΩ. ICPMAX is 5 mA. 31 CEXT4 A capacitor connected to this pin is used to roll off noise from the VCO. It should be decoupled to AGND with a value of 10 nF. 32 CEXT3 A capacitor connected to this pin is used to roll off noise from the VCO. It should be decoupled to AGND with a value of 10 nF. 33, 34 RxBBQN, RxBBQP Output/Complementary Filtered Quadrature Signals from the Receive Filter Stage. The filtered output is passed to the baseband MxFE chip. 35, 36 RxBBIP, RxBBIN Output/Complementary Filtered In-Phase from the Receive Filter Stage. The filtered output is passed to the baseband MxFE chip. 38 CE Chip Enable. A Logic 0 on this pin powers down the device. A Logic 1 on this pin enables the device depending on the status of the power-down bits. 39 SCLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the SCLK rising edge. This is a high impedance CMOS input. 40 SDATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a high impedance CMOS input. 41 SLE Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into one of the four latches; the latch uses the control bits. 42 MUXOUT This multiplexer output allows either the PLL lock detect, the scaled VCO frequency, or the scaled PLL reference frequency to be accessed externally. 43 OVF A rising edge on this pin drops the gain of the Rx path by 6 dB. This is used to rapidly drop the gain if the ADC detects an overload. 45 NC No Connect. 47, 48 RxINQP, RxINQN Input/Complementary Quadrature Input to the Receive Filter Stage. |
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