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CS230002-CZZ Datasheet(PDF) 1 Page - Cirrus Logic |
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CS230002-CZZ Datasheet(HTML) 1 Page - Cirrus Logic |
1 / 3 page Copyright © Cirrus Logic, Inc. 2008 (All Rights Reserved) http://www.cirrus.com Advance Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. 1x, 2x, 4x, and 8x Clock Multiplier with Internal LCO Features Clock Multiplier / Jitter Reduction – Generates a Low Jitter 6 - 75 MHz Clock from a Jittery 750 kHz to 30 MHz Clock Source Internal LCO Reference Clock 128 Hz Loop Filter Bandwidth Selectable Multiplication Factors – 1x, 2x, 4x, and 8x Output Enable Pin Lock Indicator Minimal Board Space Required – No External Analog Loop-filter Components General Description The CS2300-02 is an extremely versatile system clock- ing device that utilizes a programmable phase lock loop. The CS2300-02 is based on a hybrid analog-digital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL. This architecture allows for generation of a low-jitter clock relative to an external noisy synchroniza- tion clock with frequencies as low as 750 kHz. The CS2300-02 is a CS2300-OTP device that has been pre- configured at the factory. There are three hardware con- figuration pins available for mode and feature selection. Ordering Information The CS2300-02 is available in a 10-pin MSOP package in Commercial (-10°C to +70°C) grade. Customer de- velopment kits are also available for custom device prototyping and device evaluation. Please see “Order- ing Information” on page 2 for complete details. Pin-Out Diagram Hardware Controls Settings 1 2 3 4 5 6 7 8 9 10 FILTP CLK_OUT GND VD FILTN OUT_EN M1 M0 LOCK CLK_IN M1 M0 PLL_OUT 00 1x CLK_IN 01 2x CLK_IN 10 4x CLK_IN 11 8x CLK_IN OUT_EN CLK_OUT 0 Enabled 1 High Impedance 6 MHz to 75 MHz PLL Output 3.3 V Fractional-N Frequency Synthesizer 128 Hz BW Digital PLL & Fractional N Logic Output to Input Clock Ratio N 750 kHz to 30 MHz Frequency Reference LCO M[1:0] 00=1x 01=2x 10=4x 11=8x Ratio Selection PLL Lock Indicator Output Enable/Disable FILTP FILTN 0.1 µF CLK_IN M1 M0 OUT_EN LOCK VD 0.1 µF 1 µF GND CLK_OUT February '08 PS855A1 CS2300-02 |
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