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CDCE62005 Datasheet(PDF) 8 Page - Texas Instruments

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No. de pieza CDCE62005
Descripción Electrónicos  Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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CDCE62005 Datasheet(HTML) 8 Page - Texas Instruments

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Output Block
/1,2,3,4,5
UxP
UxN
/1 - /8
/2
DigitalPhase Adjust
(7 -bits )
PRI_IN
SEC_IN
SMART_MUX
SYNTH
Sync
Pulse
Enable
LVDS
ClockDividerModule0-4
LVPECL
Output
MUX
Control
OutputBufferControl
OutputDivider(7-bits)
DigitalPhase Adjust(7-bits)
SyncPulse
(internallygenerated)
Enable
From
Output
MUX
To
Output
Buffer
CDCE62005
SCAS862 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
Each of the five identical output blocks incorporates an output multiplexer, a clock divider module, and a
universal output array as shown.
Figure 6. CDCE62005 Output Block (1 of 5)
Clock Divider Module 0–4
The following shows a simplified version of a Clock Divider Module (CDM). If an individual clock output channel
is not used, then the user should disable the CDM and Output Buffer for the unused channel to save device
power. Each channel includes two 7-bit registers to control the divide ratio used and the clock phase for each
output. The output divider supports divide ratios from divide by 1 (bypass the divider) to divide by 80; the divider
does not support all integer values between 1 and 80. Refer to Table 23 for a complete list of divide ratios
supported.
Figure 7. CDCE62005 Output Divider Module (1 of 5)
8
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