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SM3-038.88M Datasheet(PDF) 4 Page - Connor-Winfield Corporation |
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SM3-038.88M Datasheet(HTML) 4 Page - Connor-Winfield Corporation |
4 / 36 page Data Sheet #: TM052 Page 4 of 36 Rev: 03 Date: 11/07/08 © Copyright 2008 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Register Map Table 3 Address Reg Name Description Type 0x00 Chip_ID_Low Low byte of chip ID R 0x01 Chip_ID_High High byte of chip ID R 0x02 Chip_Revision Chip revision number R 0x03 Bandwidth Bandwidth Select R/W 0x04 Ctl_Mode Manual or automatic selection of Op_Mode,BITS clock output frequency R/W indication, and frame/multi-frame sync pulse width mode control 0x05 Op_Mode Master Free Run, Locked, or Hold Over mode, or Slave mode R/W 0x06 Max_Pullin_Range Maximum pull-in range in 0.1 ppm units R/W 0x07 M/S REF_Activity Cross Reference activity R 0x08 Ref_Activity Activities of 4 reference inputs R 0x09 Ref_Pullin_Sts In or out of pull-in range of 4 reference inputs R 0x0a Ref_Qualified Qualification status of 4 reference inputs R 0x0b Ref_Mask Availability mask for 4 reference inputs R/W 0x0c Ref_Available Availability of 4 reference inputs R Pin Diagram Figure 2 SM3 1 14 15 LOS LOL M/S REF REF1 REF2 REF3 REF4 TDI TMS TRST BITS_CLK M/S_OUT OUTPUT1 VPP MASTER SELECT SPI_INT SPI_OUT RESET SPI_ENBL Vcc SPI_IN SPI_CLK GND TCK TDO HOLD_GOOD T1/E1 VPN 2 3 4 5 6 7 8 9 10 11 12 13 16 17 18 19 20 21 22 23 24 25 26 27 28 (TOP VIEW) |
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