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TC7126ACLW Datasheet(PDF) 6 Page - TelCom Semiconductor, Inc |
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TC7126ACLW Datasheet(HTML) 6 Page - TelCom Semiconductor, Inc |
6 / 13 page 3-222 TELCOM SEMICONDUCTOR, INC. 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7126 TC7126A analog gates close a feedback loop around the integrator and comparator. This loop permits comparator offset volt- age error compensation. The voltage level established on CAZ compensates for device offset voltages. The auto-zero phase residual is typically 10 µV to 15 µV. The auto-zero cycle length is 1000 to 3000 clock periods. Signal Integration Phase The auto-zero loop is entered and the internal differen- tial inputs connect to VIN+ and VIN–. The differential input signal is integrated for a fixed time period. The TC7126A signal integration period is 1000 clock periods, or counts. The externally-set clock frequency is 4 before clocking the internal counters. The integration time period is: tSI = 1000, where fOSC = external clock frequency. The differential input voltage must be within the device common-mode range when the converter and measured system share the same power supply common (ground). If the converter and measured system do not share the same power supply common, VIN– should be tied to analog com- mon. Polarity is determined at the end of signal integrate phase. The sign bit is a true polarity indication, in that signals less than 1 LSB are correctly determined. This allows precision null detection limited only by device noise and auto-zero residual offsets. Reference Integrate Phase The third phase is reference integrate, or deintegrate. VIN– is internally connected to analog common and VIN+ is connected across the previously-charged reference capaci- tor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal and is between 0 and 2000 internal clock periods. The digital reading displayed is: 1000 DIGITAL SECTION The TC7126A contains all the segment drivers neces- sary to directly drive a 3-1/2 digit LCD. An LCD backplane driver is included. The backplane frequency is the external clock frequency 800. For 3 conversions per second the backplane frequency is 60 Hz with a 5V nominal amplitude. 4 fOSC VIN VREF 30 20 10 0 0.1/t 1/t 10/t INPUT FREQUENCY t = MEASUREMENT PERIOD For a constant VIN: VIN = VR . tRI tSI The dual-slope converter accuracy is unrelated to the integrating resistor and capacitor values, as long as they are stable during a measurement cycle. Noise immunity is an inherent benefit. Noise spikes are integrated, or averaged, to zero during integration periods. Integrating ADCs are immune to the large conversion errors that plague succes- sive approximation converters in high-noise environments. Interfering signals with frequency components at multiples of the averaging period will be attenuated. Integrating ADCs commonly operate with the signal integration period set to a multiple of the 50 Hz/60 Hz power line period. ANALOG SECTION In addition to the basic integrate and deintegrate dual- slope cycles discussed above, the TC7126A design incor- porates an auto-zero cycle. This cycle removes buffer amplifier, integrator, and comparator offset voltage error terms from the conversion. A true digital zero reading results without external adjusting potentiometers. A complete con- version consists of three phases: (1) Auto-zero phase (2) Signal integrate phase (3) Reference integrate phase Auto-Zero Phase During the auto-zero phase, the differential input signal is disconnected from the circuit by opening internal analog gates. The internal nodes are shorted to analog common (ground) to establish a zero input condition. Additional Figure 2. Normal-Mode Rejection of Dual-Slope Converter |
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