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MC-ACT-16550-VLOG Datasheet(PDF) 6 Page - Actel Corporation |
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MC-ACT-16550-VLOG Datasheet(HTML) 6 Page - Actel Corporation |
6 / 9 page SIGNAL NAMES Signal Direction Description CLK Input The primary clock used for all circuits in this interface. RESET Input Active-high asynchronous reset. START Input Strobe to start TWSI bus cycle. ENABLE Input WHEN ASSERTED THE CORE WILL BE ENABLED. THIS MUST BE DRIVEN FROM A REGISTER. STDFAST_N Input Select TWSI transfer speed mode. Set to ‘1’ for standard (100 kHz) or set to ‘0’ for fast (400 kHz). DATA_IN[7:0] Input The data input vector. ADDR_IN[6:0] Input The address input vector. TWSI_CMD[2:0] Input The command input vector. Tells the core what TWSI command to perform (read/write, stop, repeated start). CFG[127:0] Input MC-TWSI configuration vector. Configures the options for the MC-TWSI core (SCL timer values, TWSI mode, etc.). DATA_VLD Output Asserted for one clock cycle to indicate a data byte has been received on the TWSI bus and is available on DATA_OUT. REQ_DATA Output Asserted for one clock cycle indicate a data byte is requested when sourcing data. Can be used to incre- ment a data pointer. FIRST_BYTE Output Indicates the byte just received is the first data byte (of what may be a burst). Can be used as an enable to latch the data byte (on DATA_OUT) as an offset in to a register or memory array. STATUS[5:0] Output The STATUS bits are always available and are cleared when START is strobed. DATA_OUT[7:0] Output The DATA_OUT port contains the data byte just received on the TWSI bus and is qualified with DATA_VLD at the completion of a TWSI data phase. SDA_IN Input This is the serial data line open collector input. SDA_OUT Output This is the serial data line open collector output. SCL_IN Input This is the serial clock line open collector input. SCL_OUT Output This is the serial clock line open collector output. SDA External TWSI serial data line. SCL External TWSI serial clock line. Table 2: Core and External Signal Pinout |
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