CDCF2510

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS628B – APRIL 1999 REVISED NOVEMBER 1999

4

POST OFFICE BOX 655303

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–0.5 V to 4.6 V

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–0.5 V to 6.5 V

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Voltage range applied to any output in the high or low state,

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–50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±50 mA

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±50 mA

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±100 mA

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0.7 W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65

°C to 150°C

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† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. AVCC must not exceed VCC.

2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

3. This value is limited to 4.6 V maximum.

4. The maximum package power dissipation is calculated using a junction temperature of 150

°C and a board trace length of 750 mils.

For more information, refer to the

Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data

Book, literature number SCBD002.

recommended operating conditions (see Note 5)

MIN

MAX

UNIT

VCC, AVCC Supply voltage

3

3.6

V

VIH

High-level input voltage

2

V

VIL

Low-level input voltage

0.8

V

VI

Input voltage

0

VCC

V

IOH

High-level output current

–12

mA

IOL

Low-level output current

12

mA

TA

Operating free-air temperature

0

85

°C

NOTE 5: Unused inputs must be held high or low to prevent them from floating.

timing requirements over recommended ranges of supply voltage and operating free-air

temperature

MIN

MAX

UNIT

fclk

Clock frequency

25

140

MHz

Input clock duty cycle

40%

60%

Stabilization time†

1

ms

† Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a

fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,

and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under

SSC application.