DAC7800, 7801, 7802

3

SBAS005A

www.ti.com

AC PERFORMANCE

OUTPUT OP AMP IS OPA602.

NOTE: (1) Ensured but not tested.

DAC7800, 7801, 7802K

DAC7800, 7801, 7802L

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

OUTPUT CURRENT SETTLING TIME

To 0.01% of Full-Scale

0.4

0.8

✻✻

µs

DIGITAL-TO-ANALOG GLITCH IMPULSE

0.9

✻

nV-s

AC FEEDTHROUGH

–75

–72

✻✻

dB

OUTPUT CAPACITANCE

DAC Loaded with All 0s

30

50

✻✻

pF

DAC Loaded with All 1s

70

100

✻✻

pF

CHANNEL-TO-CHANNEL ISOLATION

–90

–94

✻✻

dB

Both DACs Loaded with 1s

–90

–101

✻✻

dB

Both DACs Loaded with 1s

DIGITAL CROSSTALK

Full-Scale Transition

0.9

✻

nV-s

✻ Same specification as for DAC7800, 7801, and 7802K.

DAC7800

BLOCK DIAGRAM

DAC A

DAC B

DAC A Register

12

12

12

UPD B

I

AGND B

R

V

V

R

I

AGND A

UPD A

OUT B

FB B

REF B

REF A

FB A

OUT A

12

V

DD

9

DGND

10

15

16

14

13

4

3

2

1

6

DAC B Register

Bit 0

Bit 11

Bit 12

Bit 23

7

11

CLR

12

DAC7800

Data

In

5

CLK

8

CS

PIN CONFIGURATION

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

AGND A

CLK

UPD A

Data In

CS

AGND B

I

R

V

V

CLR

UPD B

DGND

OUT A

FB A

REF A

OUT B

DAC7800

I

R

V

FB B

REF B

DD

CLK

UPD A

UPD B

CS

CLR

FUNCTION

XXXX

0

All register contents set to 0’s (asynchronous).

X

X

X

1

X

No data transfer.

X

X

0

1

Input data is clocked into input register (location Bit 23) and previous data shifts.

X

0101

Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A.

X

1001

Input register bits 11 (LSB) - 0 (MSB) are loaded into DAC B.

X

0001

Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A, and input register bits 11 (LSB) - 0 (MSB)

are loaded into DAC B.

X = Don’t care.

means falling edge triggered.

LOGIC TRUTH TABLE

Top View

DIP