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CDK8307DITQ80 Datasheet(PDF) 8 Page - Cadeka Microcircuits LLC. |
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CDK8307DITQ80 Datasheet(HTML) 8 Page - Cadeka Microcircuits LLC. |
8 / 29 page ©2009 CADEKA Microcircuits LLC www.cadeka.com 8 PRELIMINARY Data Sheet Pin Assignments (Continued) Pin No. Pin Name Description 16 PD Power-down input 19 LCKP LVDS bit clock, positive output 20 LCKN LVDS bit clock, negative output 21 D1P LVDS channel 1, positive output 22 D1N LVDS channel 1, negative output 23 D2P LVDS channel 2, positive output 24 D2N LVDS channel 2, negative output 27 D3P LVDS channel 3, positive output 28 D3N LVDS channel 3, negative output 29 D4P LVDS channel 4, positive output 30 D4N LVDS channel 4, negative output 31 D5P LVDS channel 5, positive output 32 D5N LVDS channel 5, negative output 33 D6P LVDS channel 6, positive output 34 D6N LVDS channel 6, negative output 37 D7P LVDS channel 7, positive output 38 D7N LVDS channel 7, negative output 39 D8P LVDS channel 8, positive output 40 D8N LVDS channel 8, negative output 41 FCLKP LVDS frame clock (1x), positive output 42 FCLKN LVDS frame clock (1x), negative output 45 RESETN Reset SPI interface 62, 64, 66, 67, 69 NC Not connected 65 VCM Common mode output pin, 0.5 AVDD 71 CLKP Positive differential input clock 72 CLKN Negative differential input clock. 75 OVDD Digital CMOS inputs supply voltage (1.7V to 3.6V) 76 CSN Chip select enable. Active low. 77 SDATA Serial data input 78 SCLK Serial clock input |
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