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AD7846AP Datasheet(PDF) 10 Page - Analog Devices |
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AD7846AP Datasheet(HTML) 10 Page - Analog Devices |
10 / 16 page REV. E –10– AD7846 AD7846 DAC1 RIN VOUT DGND VREF+ VREF– DB0 DB15 –15V AD588 VH AD7846 DAC2 RIN VOUT DGND VREF+ VREF– DB0 DB15 AD7846 DAC3 RIN VOUT DGND VREF+ VREF– DB0 DB15 AD7846 DAC4 RIN VOUT DGND VREF+ VREF– DB0 DB15 COMPARE DATA AND DON'T CARE DATA PERIOD GENERATION AND DELAY DUT FORMATTER D D INH INH VL AD345 COMPARE REGISTER AD9687 DC PARAMETRICS +15V R1 39k STORED DATA AND INHIBIT PATTERN Figure 21. Digital Test System with 16-Bit Performance TEST APPLICATION Figure 21 shows the AD7846 in an Automatic Test Equipment application. The readback feature of the AD7846 is very useful in these systems. It allows the designer to eliminate phantom memory used for storing DAC contents and increases system reliability since the phantom memory is now effectively on chip with the DAC. The readback feature is used in the following manner to control a data transfer. First, write the desired 16-bit word to the DAC input latch using the CS and R/W inputs. Verify that correct data has been received by reading back the latch contents. Now, the data transfer can be completed by bringing the asynchronous LDAC control line low. The analog equivalent of the digital word now appears at the DAC output. In Figure 21, each pin on the Device Under Test can be an input or output. The AD345 is the pin driver for the digital inputs, and the AD9687 is the receiver for the digital outputs. The digital control circuitry determines the signal timing and format. DACs 1 and 2 set the pin driver voltage levels (VH and VL), and DACs 3 and 4 set the receiver voltage levels. The pin drivers used in ATE systems normally have a nonlinearity between input and output. The 16-bit resolution of the AD7846 allows compensation for these input/output nonlinearities. The dc parametrics shown in Figure 21 measure the voltage at the device pin and feed this back to the system processor. The pin voltage can thus be fine-tuned by incrementing or decrementing DACs 1 and 2 under system processor control. |
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