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TL16C550AN Datasheet(PDF) 7 Page - Texas Instruments |
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TL16C550AN Datasheet(HTML) 7 Page - Texas Instruments |
7 / 31 page TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS057D – AUGUST 1989 – REVISED MARCH 1996 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 system timing requirements over recommended ranges of supply voltage and operating free-air temperature ALT. SYMBOL FIGURE MIN MAX UNIT tcR Cycle time, read (tw7 + td8 + td9) RC 175 ns tcW Cycle time, write (tw6 + td5 + td6) WC 175 ns tw5 Pulse duration, ADS low tADS 2, 3 15 ns tw6 Pulse duration, write strobe tWR 2 80 ns tw7 Pulse duration, read strobe tRD 3 80 ns tw8 Pulse duration, master reset tMR 1 µs tsu1 Setup time, address valid before ADS ↑ tAS 2, 3 15 ns tsu2 Setup time, CS before ADS ↑ tCS 2, 3 15 ns tsu3 Setup time, data valid before WR1 ↓ or WR2 ↑ tDS 2 15 ns th1 Hold time, address low after ADS ↑ tAH 2, 3 0 ns th2 Hold time, CS valid after ADS ↑ tCH 2, 3 0 ns th3 Hold time, CS valid after WR1 ↑ or WR2 ↓ tWCS 2 20 ns th4§ Hold time, address valid after WR1 ↑ or WR2 ↓ tWA 2 20 ns th5 Hold time, data valid after WR1 ↑ or WR2 ↓ tDH 2 15 ns th6 Hold time, CS valid after RD1 ↑ or RD2↓ tRCS 3 20 ns th7§ Hold time, address valid after RD1 ↑ or RD2↓ tRA 3 20 ns td4§ Delay time, CS valid before WR1 ↓ or WR2 ↑ tCSW 2 15 ns td5§ Delay time, address valid before WR1 ↓ or WR2 ↑ tAW 2 15 ns td6§ Delay time, write cycle, WR1 ↑ or WR2 ↓ to ADS ↓ tWC 2 80 ns td7§ Delay time, CS valid to RD1 ↓ or RD2↑ tCSR 3 15 ns td8§ Delay time, address valid to RD1 ↓ or RD2↑ tAR 3 15 ns td9 Delay time, read cycle, RD1 ↑ or RD2↓ to ADS↓ tRC 3 80 ns § Applicable only when ADS is tied low. system switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 2) PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT tw1 Pulse duration, clock high tXH 1 f = 9 MHz maximum 50 ns tw2 Pulse duration, clock low tXL 1 f = 9 MHz maximum 50 ns td10 Delay time, RD1 ↓ or RD2↑ to data valid tRVD 3 CL = 100 pF 60 ns td11 Delay time, RD1 ↑ or RD2↓ to floating data tHZ 3 CL = 100 pF 0 60 ns tdis(R) Disable time, RD1 ↓↑ or RD2↑↓ to DDIS↑↓ tRDD 3 CL = 100 pF 60 ns NOTE 2: Charge and discharge time is determined by VOL, VOH, and external loading. baud generator switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT tw3 Pulse duration, BAUDOUT low tLW 1 f = 9 MHz, CLK ÷ 2, CL = 100 pF 80 ns tw4 Pulse duration, BAUDOUT high tHW 1 f = 9 MHz, CLK ÷ 2, CL = 100 pF 100 ns td1 Delay time, XIN ↑ to BAUDOUT↑ tBLD 1 CL = 100 pF 125 ns td2 Delay time, XIN ↑↓ to BAUDOUT↓ tBHD 1 CL = 100 pF 125 ns |
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